Patents by Inventor Pohsiang Hsu

Pohsiang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10390037
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: August 20, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Patent number: 10368065
    Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 30, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Pohsiang Hsu
  • Patent number: 10341688
    Abstract: Various new and non-obvious apparatus and methods for using frame caching to improve packet loss recovery are disclosed. One of the disclosed embodiments is a method for using periodical and synchronized frame caching within an encoder and its corresponding decoder. When the decoder discovers packet loss, it informs the encoder which then generates a frame based on one of the shared frames stored at both the encoder and the decoder. When the decoder receives this generated frame it can decode it using its locally cached frame.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: July 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chih-Lung Lin, Minghui Xia, Pohsiang Hsu, Shankar Regunathan, Thomas W. Holcomb
  • Publication number: 20190075317
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Application
    Filed: November 1, 2018
    Publication date: March 7, 2019
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Patent number: 10123038
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: November 6, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Patent number: 10075731
    Abstract: Techniques and tools for video coding/decoding with sub-block transform coding/decoding and re-oriented transforms are described. For example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding. The video encoder may determine the transform sizes as well as switching levels (e.g., frame, macroblock, or block) in a closed loop evaluation of the different transform sizes and switching levels. When a video encoder or decoder uses spatial extrapolation from pixel values in a causal neighborhood to predict pixel values of a block of pixels, the encoder/decoder can use a re-oriented transform to address non-stationarity of prediction residual values.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: September 11, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Ming-Chieh Lee
  • Patent number: 9866871
    Abstract: Various new and non-obvious apparatus and methods for using frame caching to improve packet loss recovery are disclosed. One of the disclosed embodiments is a method for using periodical and synchronized frame caching within an encoder and its corresponding decoder. When the decoder discovers packet loss, it informs the encoder which then generates a frame based on one of the shared frames stored at both the encoder and the decoder. When the decoder receives this generated frame it can decode it using its locally cached frame.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: January 9, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chih-Lung Lin, Minghui Xia, Pohsiang Hsu, Shankar Regunathan, Thomas W. Holcomb
  • Publication number: 20170374362
    Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.
    Type: Application
    Filed: September 8, 2017
    Publication date: December 28, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Pohsiang Hsu
  • Patent number: 9774852
    Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: September 26, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Pohsiang Hsu
  • Publication number: 20170078658
    Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 16, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Pohsiang Hsu
  • Patent number: 9538189
    Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: January 3, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Pohsiang Hsu
  • Publication number: 20160373780
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8x8, 8x4, and 4x8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Publication number: 20160366445
    Abstract: Various new and non-obvious apparatus and methods for using frame caching to improve packet loss recovery are disclosed. One of the disclosed embodiments is a method for using periodical and synchronized frame caching within an encoder and its corresponding decoder. When the decoder discovers packet loss, it informs the encoder which then generates a frame based on one of the shared frames stored at both the encoder and the decoder. When the decoder receives this generated frame it can decode it using its locally cached frame.
    Type: Application
    Filed: April 11, 2016
    Publication date: December 15, 2016
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Chih-Lung Lin, Minghui Xia, Pohsiang Hsu, Shankar Regunathan, Thomas W. Holcomb
  • Patent number: 9479796
    Abstract: A video codec provides for encoding and decoding pictures of a video sequence at various coded resolutions, such that pictures can be encoded at lower coded resolutions based on bit rate or other constraints while maintaining a consistent display resolution. The video codec employs a coding syntax where a maximum coded resolution is signaled at the sequence level of the syntax hierarchy, whereas a lower coded resolution is signaled at the entry point level for a segment of one or more intra-coded frames and frames predictively encoded based thereon. This allows the use of a separate out-of-loop resampler after the decoder to up-sample the pictures to the display resolution.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: October 25, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Chih-Lung Lin, Sridhar Srinivasan, Pohsiang Hsu
  • Patent number: 9432686
    Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: August 30, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
  • Publication number: 20160227215
    Abstract: Techniques and tools for video coding/decoding with sub-block transform coding/decoding and re-oriented transforms are described. For example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding. The video encoder may determine the transform sizes as well as switching levels (e.g., frame, macroblock, or block) in a closed loop evaluation of the different transform sizes and switching levels. When a video encoder or decoder uses spatial extrapolation from pixel values in a causal neighborhood to predict pixel values of a block of pixels, the encoder/decoder can use a re-oriented transform to address non-stationarity of prediction residual values.
    Type: Application
    Filed: December 30, 2015
    Publication date: August 4, 2016
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Ming-Chieh Lee
  • Patent number: 9313501
    Abstract: Various new and non-obvious apparatus and methods for using frame caching to improve packet loss recovery are disclosed. One of the disclosed embodiments is a method for using periodical and synchronized frame caching within an encoder and its corresponding decoder. When the decoder discovers packet loss, it informs the encoder which then generates a frame based on one of the shared frames stored at both the encoder and the decoder. When the decoder receives this generated frame it can decode it using its locally cached frame.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 12, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chih-Lung Lin, Minghui Xia, Pohsiang Hsu, Shankar Regunathan, Thomas W. Holcomb
  • Patent number: 9258570
    Abstract: Techniques and tools for video coding/decoding with sub-block transform coding/decoding and re-oriented transforms are described. For example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding. The video encoder may determine the transform sizes as well as switching levels (e.g., frame, macroblock, or block) in a closed loop evaluation of the different transform sizes and switching levels. When a video encoder or decoder uses spatial extrapolation from pixel values in a causal neighborhood to predict pixel values of a block of pixels, the encoder/decoder can use a re-oriented transform to address non-stationarity of prediction residual values.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 9, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sridhar Srinivasan, Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Ming-Chieh Lee
  • Publication number: 20150334416
    Abstract: A video codec provides for encoding and decoding pictures of a video sequence at various coded resolutions, such that pictures can be encoded at lower coded resolutions based on bit rate or other constraints while maintaining a consistent display resolution. The video codec employs a coding syntax where a maximum coded resolution is signaled at the sequence level of the syntax hierarchy, whereas a lower coded resolution is signaled at the entry point level for a segment of one or more intra-coded frames and frames predictively encoded based thereon. This allows the use of a separate out-of-loop resampler after the decoder to up-sample the pictures to the display resolution.
    Type: Application
    Filed: May 26, 2015
    Publication date: November 19, 2015
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Chih-Lung Lin, Sridhar Srinivasan, Pohsiang Hsu
  • Publication number: 20150288962
    Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Sridhar Srinivasan, Pohsiang Hsu