Patents by Inventor Pohsiang Hsu
Pohsiang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10341688Abstract: Various new and non-obvious apparatus and methods for using frame caching to improve packet loss recovery are disclosed. One of the disclosed embodiments is a method for using periodical and synchronized frame caching within an encoder and its corresponding decoder. When the decoder discovers packet loss, it informs the encoder which then generates a frame based on one of the shared frames stored at both the encoder and the decoder. When the decoder receives this generated frame it can decode it using its locally cached frame.Type: GrantFiled: April 11, 2016Date of Patent: July 2, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Chih-Lung Lin, Minghui Xia, Pohsiang Hsu, Shankar Regunathan, Thomas W. Holcomb
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Publication number: 20190075317Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.Type: ApplicationFiled: November 1, 2018Publication date: March 7, 2019Applicant: Microsoft Technology Licensing, LLCInventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
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Patent number: 10123038Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.Type: GrantFiled: August 29, 2016Date of Patent: November 6, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
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Patent number: 10075731Abstract: Techniques and tools for video coding/decoding with sub-block transform coding/decoding and re-oriented transforms are described. For example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding. The video encoder may determine the transform sizes as well as switching levels (e.g., frame, macroblock, or block) in a closed loop evaluation of the different transform sizes and switching levels. When a video encoder or decoder uses spatial extrapolation from pixel values in a causal neighborhood to predict pixel values of a block of pixels, the encoder/decoder can use a re-oriented transform to address non-stationarity of prediction residual values.Type: GrantFiled: December 30, 2015Date of Patent: September 11, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Sridhar Srinivasan, Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Ming-Chieh Lee
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Patent number: 9866871Abstract: Various new and non-obvious apparatus and methods for using frame caching to improve packet loss recovery are disclosed. One of the disclosed embodiments is a method for using periodical and synchronized frame caching within an encoder and its corresponding decoder. When the decoder discovers packet loss, it informs the encoder which then generates a frame based on one of the shared frames stored at both the encoder and the decoder. When the decoder receives this generated frame it can decode it using its locally cached frame.Type: GrantFiled: January 17, 2014Date of Patent: January 9, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Chih-Lung Lin, Minghui Xia, Pohsiang Hsu, Shankar Regunathan, Thomas W. Holcomb
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Publication number: 20170374362Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.Type: ApplicationFiled: September 8, 2017Publication date: December 28, 2017Applicant: Microsoft Technology Licensing, LLCInventors: Sridhar Srinivasan, Pohsiang Hsu
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Patent number: 9774852Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.Type: GrantFiled: November 3, 2016Date of Patent: September 26, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Sridhar Srinivasan, Pohsiang Hsu
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Publication number: 20170078658Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.Type: ApplicationFiled: November 3, 2016Publication date: March 16, 2017Applicant: Microsoft Technology Licensing, LLCInventors: Sridhar Srinivasan, Pohsiang Hsu
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Patent number: 9538189Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.Type: GrantFiled: June 22, 2015Date of Patent: January 3, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Sridhar Srinivasan, Pohsiang Hsu
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Publication number: 20160373780Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8x8, 8x4, and 4x8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.Type: ApplicationFiled: August 29, 2016Publication date: December 22, 2016Applicant: Microsoft Technology Licensing, LLCInventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
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Publication number: 20160366445Abstract: Various new and non-obvious apparatus and methods for using frame caching to improve packet loss recovery are disclosed. One of the disclosed embodiments is a method for using periodical and synchronized frame caching within an encoder and its corresponding decoder. When the decoder discovers packet loss, it informs the encoder which then generates a frame based on one of the shared frames stored at both the encoder and the decoder. When the decoder receives this generated frame it can decode it using its locally cached frame.Type: ApplicationFiled: April 11, 2016Publication date: December 15, 2016Applicant: Microsoft Technology Licensing, LLCInventors: Chih-Lung Lin, Minghui Xia, Pohsiang Hsu, Shankar Regunathan, Thomas W. Holcomb
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Patent number: 9479796Abstract: A video codec provides for encoding and decoding pictures of a video sequence at various coded resolutions, such that pictures can be encoded at lower coded resolutions based on bit rate or other constraints while maintaining a consistent display resolution. The video codec employs a coding syntax where a maximum coded resolution is signaled at the sequence level of the syntax hierarchy, whereas a lower coded resolution is signaled at the entry point level for a segment of one or more intra-coded frames and frames predictively encoded based thereon. This allows the use of a separate out-of-loop resampler after the decoder to up-sample the pictures to the display resolution.Type: GrantFiled: May 26, 2015Date of Patent: October 25, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Thomas W. Holcomb, Chih-Lung Lin, Sridhar Srinivasan, Pohsiang Hsu
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Patent number: 9432686Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.Type: GrantFiled: November 11, 2014Date of Patent: August 30, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Pohsiang Hsu, Chih-Lung Lin, Ming-Chieh Lee, Thomas W. Holcomb, Sridhar Srinivasan
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Publication number: 20160227215Abstract: Techniques and tools for video coding/decoding with sub-block transform coding/decoding and re-oriented transforms are described. For example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding. The video encoder may determine the transform sizes as well as switching levels (e.g., frame, macroblock, or block) in a closed loop evaluation of the different transform sizes and switching levels. When a video encoder or decoder uses spatial extrapolation from pixel values in a causal neighborhood to predict pixel values of a block of pixels, the encoder/decoder can use a re-oriented transform to address non-stationarity of prediction residual values.Type: ApplicationFiled: December 30, 2015Publication date: August 4, 2016Applicant: Microsoft Technology Licensing, LLCInventors: Sridhar Srinivasan, Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Ming-Chieh Lee
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Patent number: 9313501Abstract: Various new and non-obvious apparatus and methods for using frame caching to improve packet loss recovery are disclosed. One of the disclosed embodiments is a method for using periodical and synchronized frame caching within an encoder and its corresponding decoder. When the decoder discovers packet loss, it informs the encoder which then generates a frame based on one of the shared frames stored at both the encoder and the decoder. When the decoder receives this generated frame it can decode it using its locally cached frame.Type: GrantFiled: September 13, 2012Date of Patent: April 12, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Chih-Lung Lin, Minghui Xia, Pohsiang Hsu, Shankar Regunathan, Thomas W. Holcomb
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Patent number: 9258570Abstract: Techniques and tools for video coding/decoding with sub-block transform coding/decoding and re-oriented transforms are described. For example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding. The video encoder may determine the transform sizes as well as switching levels (e.g., frame, macroblock, or block) in a closed loop evaluation of the different transform sizes and switching levels. When a video encoder or decoder uses spatial extrapolation from pixel values in a causal neighborhood to predict pixel values of a block of pixels, the encoder/decoder can use a re-oriented transform to address non-stationarity of prediction residual values.Type: GrantFiled: April 22, 2014Date of Patent: February 9, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Sridhar Srinivasan, Thomas W. Holcomb, Chih-Lung Lin, Pohsiang Hsu, Ming-Chieh Lee
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Publication number: 20150334416Abstract: A video codec provides for encoding and decoding pictures of a video sequence at various coded resolutions, such that pictures can be encoded at lower coded resolutions based on bit rate or other constraints while maintaining a consistent display resolution. The video codec employs a coding syntax where a maximum coded resolution is signaled at the sequence level of the syntax hierarchy, whereas a lower coded resolution is signaled at the entry point level for a segment of one or more intra-coded frames and frames predictively encoded based thereon. This allows the use of a separate out-of-loop resampler after the decoder to up-sample the pictures to the display resolution.Type: ApplicationFiled: May 26, 2015Publication date: November 19, 2015Applicant: Microsoft Technology Licensing, LLCInventors: Thomas W. Holcomb, Chih-Lung Lin, Sridhar Srinivasan, Pohsiang Hsu
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Publication number: 20150288962Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.Type: ApplicationFiled: June 22, 2015Publication date: October 8, 2015Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Sridhar Srinivasan, Pohsiang Hsu
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Patent number: 9148668Abstract: Techniques and tools for encoding and decoding motion vector information for video images are described. For example, a video encoder yields an extended motion vector code by jointly coding, for a set of pixels, a switch code, motion vector information, and a terminal symbol indicating whether subsequent data is encoded for the set of pixels. In another aspect, an encoder/decoder selects motion vector predictors for macroblocks. In another aspect, a video encoder/decoder uses hybrid motion vector prediction. In another aspect, a video encoder/decoder signals a motion vector mode for a predicted image. In another aspect, a video decoder decodes a set of pixels by receiving an extended motion vector code, which reflects joint encoding of motion information together with intra/inter-coding information and a terminal symbol. The decoder determines whether subsequent data exists for the set of pixels based on e.g., the terminal symbol.Type: GrantFiled: February 13, 2014Date of Patent: September 29, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Sridhar Srinivasan, Pohsiang Hsu, Thomas W. Holcomb, Kunal Mukerjee, Bruce Chih-Lung Lin
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Patent number: 9088785Abstract: Various techniques and tools for encoding and decoding (e.g., in a video encoder/decoder) binary information (e.g., skipped macroblock information) are described. In some embodiments, the binary information is arranged in a bit plane, and the bit plane is coded at the picture/frame layer. The encoder and decoder process the binary information and, in some embodiments, switch coding modes. For example, the encoder and decoder use normal, row-skip, column-skip, or differential modes, or other and/or additional modes. In some embodiments, the encoder and decoder define a skipped macroblock as a predicted macroblock whose motion is equal to its causally predicted motion and which has zero residual error. In some embodiments, the encoder and decoder use a raw coding mode to allow for low-latency applications.Type: GrantFiled: May 30, 2014Date of Patent: July 21, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Sridhar Srinivasan, Pohsiang Hsu