Abstract: A nuclear battery module is adapted for a nuclear battery. The nuclear battery module includes a radioactive unit and at least one energy conversion unit. The radioactive unit includes a soft substrate and at least one radioactive layer disposed on the soft substrate. The at least one radioactive layer includes a ?-ray source. The at least one energy conversion unit includes a flexible carrier layer, an N-type semiconductor layer disposed on the flexible carrier layer, and a P-type semiconductor layer disposed on the N-type semiconductor layer opposite to the flexible carrier layer. The at least one energy conversion unit is disposed on the radioactive unit in a manner such that the flexible carrier layer is proximate to the radioactive unit.

Abstract: A layout pattern of static random-access memory (SRAM) includes a substrate, a plurality of diffusion regions and a plurality of gate structures are located on the substrate, each diffusion region includes a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region, and each gate structure spans the plurality of diffusion regions. The plurality of gate structures include a first gate structure, the first gate structure includes a first L-shaped portion, which spans the first diffusion region and the fifth diffusion region and forms a first pull-down transistor (PD1), the first diffusion region is adjacent to and in direct contact with the fifth diffusion region.

Abstract: A testing circuitry includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is configured to generate an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generate a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal. The first clock adjustment circuit is configured to generate a first test clock signal according to the first control signal and the internal clock signal, in order to test a multicycle path circuit. The plurality of first bits are to set a first pulse of the first test clock signal, in order to prevent the multicycle path circuit from occurring a timing violation.

Abstract: A semiconductor device includes a control signal generating circuit, a first circuit and a second circuit. The control signal generating circuit is configured to generate a control signal. The first circuit is coupled to the control signal generating circuit and configured to receive the control signal and generate a first test pulse signal according to the control signal. The second circuit is coupled to the control signal generating circuit and the first circuit and configured to receive the control signal and generate a second test pulse signal according to the control signal. The first circuit is comprised in the first block. The second circuit is comprised in the second block. The first block and the second block are connected with each other via one or more interconnection logics and timing of the first test pulse signal and timing of the second test pulse signal are synchronized.

Abstract: A nuclear battery module is adapted for a nuclear battery. The nuclear battery module includes a radioactive unit and at least one energy conversion unit. The radioactive unit includes a soft substrate and at least one radioactive layer disposed on the soft substrate. The at least one radioactive layer includes a ?-ray source. The at least one energy conversion unit includes a flexible carrier layer, an N-type semiconductor layer disposed on the flexible carrier layer, and a P-type semiconductor layer disposed on the N-type semiconductor layer opposite to the flexible carrier layer. The at least one energy conversion unit is disposed on the radioactive unit in a manner such that the flexible carrier layer is proximate to the radioactive unit.

Abstract: A chip includes a first circuit under test, a second circuit under test, and a clock masking circuit. The first circuit under test is coupled to the second circuit under test. The clock masking circuit includes a first clock control circuit, a second clock control circuit, and an enabling circuit. The first clock control circuit is configured to provide a first clock signal for the first circuit under test according to a first enable signal and an initial clock signal. The second clock control circuit is configured to provide a second clock signal for the second circuit under test according to a second enable signal and the initial clock signal. The enabling circuit is configured to provide a first enable signal for the first clock control circuit and a second enable signal for the second clock control circuit.

Abstract: A test circuit includes a scan chain and a wrapper chain. The wrapper chain shifts in a test pattern according a first clock. The scan chain is coupled to the wrapper chain via a logic combination of a circuit under test. The wrapper chain is configured to transmit the test pattern to the scan chain via the logic combination according to a second clock in a capture phase. The wrapper chain includes a first, a second wrapper cell, and an asynchronous register. The first wrapper cell sequentially shifts in two bits of the test pattern in the shift-in phase. The second wrapper cell shifts in the first bit of the test pattern in the shift-in phase. The asynchronous register conducts the first wrapper cell to the second wrapper cell in the shift-in phase, and latches the second wrapper cell in the capture phase.

Abstract: A testing circuitry includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is configured to generate an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generate a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal. The first clock adjustment circuit is configured to generate a first test clock signal according to the first control signal and the internal clock signal, in order to test a multicycle path circuit. The plurality of first bits are to set a first pulse of the first test clock signal, in order to prevent the multicycle path circuit from occurring a timing violation.

Abstract: A scan test device includes a scan flip flop circuit and a clock gating circuit. The scan flip flop circuit is configured to receive a scan input signal according to a scan clock signal, and to output the received scan input signal to be a test signal. The clock gating circuit is configured to selectively mask the scan clock signal according to a predetermined bit of the test signal and a scan enable signal, in order to generate a test clock signal for testing at least one core circuit.

Abstract: A test circuit includes a scan chain and a wrapper chain. The wrapper chain shifts in a test pattern according a first clock. The scan chain is coupled to the wrapper chain via a logic combination of a circuit under test. The wrapper chain is configured to transmit the test pattern to the scan chain via the logic combination according to a second clock in a capture phase. The wrapper chain includes a first, a second wrapper cell, and an asynchronous register. The first wrapper cell sequentially shifts in two bits of the test pattern in the shift-in phase. The second wrapper cell shifts in the first bit of the test pattern in the shift-in phase. The asynchronous register conducts the first wrapper cell to the second wrapper cell in the shift-in phase, and latches the second wrapper cell in the capture phase.

Abstract: A semiconductor device includes a control signal generating circuit, a first circuit and a second circuit. The control signal generating circuit is configured to generate a control signal. The first circuit is coupled to the control signal generating circuit and configured to receive the control signal and generate a first test pulse signal according to the control signal. The second circuit is coupled to the control signal generating circuit and the first circuit and configured to receive the control signal and generate a second test pulse signal according to the control signal. The first circuit is comprised in the first block. The second circuit is comprised in the second block. The first block and the second block are connected with each other via one or more interconnection logics and timing of the first test pulse signal and timing of the second test pulse signal are synchronized.

Abstract: A curved display and a method for binding a cover glass of the curved display are provided. The curved display includes a display module, a frame body and a cover glass. The frame body has a first flat surface and a second flat surface opposite to the first flat surface, in which the first flat surface is adhered to the display module. The cover glass has a binding flat surface and an application surface opposite to the binding flat surface, in which the binding flat surface is adhered to the second flat surface of the frame body, and the application surface is a surface with curvature. The second flat surface of the frame body is set with a first alignment mark, and the binding flat surface of the cover glass is set with a second alignment mark, and the first alignment mark corresponds to the second alignment mark.

Abstract: A scan test device includes a scan flip flop circuit and a clock gating circuit. The scan flip flop circuit is configured to receive a scan input signal according to a scan clock signal, and to output the received scan input signal to be a test signal. The clock gating circuit is configured to selectively mask the scan clock signal according to a predetermined bit of the test signal and a scan enable signal, in order to generate a test scan clock signal for testing at least one core circuit.

Abstract: An electronic device test database generating method, comprising: (a) acquiring cell layout information of a target electronic device; (b) generating possible defect location information of the target electronic device according to the cell layout information, wherein the possible defect location information comprises at least one possible defect location of the target electronic device; (c) testing the target electronic device according to the possible defect location information to generate a testing result; and (d) generating an electronic device test database according to the testing result.

Abstract: A wafer testing machine and a method for training an artificial intelligence (AI) model to test wafers are provided. The wafer contains multiple dies. The method includes the following steps of: determining a target die from the dies; selecting multiple reference dies close to the target die based on the target die and a preset range; generating a main training data which includes a measured value of the target die and the measured value of each reference die; generating an auxiliary training data which indicates whether each reference die is a passed die or a failed die; and training the AI model using the main training data and the auxiliary training data.

Abstract: An improved insulation protection structure comprises a sensor film, a chip outline, a protective film, and an insulating cement layer. The chip outline is on the sensor film, the protective film is on the chip outline, the insulating cement layer is between the chip outline and the protective film. The insulating cement layer comprises at least one surface facing inward the chip outline, retracted toward the direction of the chip outline and forms a retracted region along at least one side of the sensor film. Area of the proposed retracted region is preferably no more than 20% of that of the total insulating cement layer, and the conventional issues such as sulphide corrosion are solved. The proposed insulating cement layer can be cured merely at room temperature, and widely used for adhesive materials including both a gel and film, thus characterized by wider application range and better industrial applicability.

Abstract: A circuit having multiple scan modes is disclosed. The circuit includes a first circuit block and a second circuit block. The first circuit block corresponds to a first scan mode of the multiple scan modes, and the first circuit block includes at least one first scan chain for receiving a test signal from an external automatic test equipment. The second circuit block corresponds to a second scan mode of the multiple scan modes, and the second circuit block includes at least one second scan chain for receiving another test signal from the external automatic test equipment. The second scan chain includes at least one specific flip-flop positioned in the first circuit block, and the specific flip-flop is configured to drive the second circuit block.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.

Abstract: A test pattern generating method for generating a test pattern for a circuit under test. The test pattern generating method comprises: (a) computing a plurality of signal delay values which a plurality of cells have due to different defects; (b) comparing the signal delay values and signal path delay information of a target circuit to generate a fault model; and (c) generate at least one test pattern according to the fault model.