Abstract: An apparatus for measuring static phase error in a delay locked loop includes a first test stage and a second test stage. The first test stage receives a reference clock, a chip clock, and a control signal. In parallel with the first test stage, the second test stage receives the reference clock, the chip clock, and a complement of the control signal. Dependent on the control signal, the first test stage outputs a first test signal, and, dependent on the complement of the control signal, the second test stage outputs a second test signal. The first test signal and the second test signal are used to generate a set of static phase error measurements dependent on values of the control signal and the complement of the control signal. By averaging the set of static phase error measurements, a static phase error is measured for the delay locked loop.

Abstract: A single edge-triggered flip-flop having an asynchronous programmable reset function is provided. Using an externally generated reset value, the single edge-triggered flip-flop may be asynchronously programmed to dynamically reset to either a logical high or a logical low. Further, a single edge-triggered flip-flop having a reduced hold time is provided. In particular, by inputting a clock signal into a slave stage of the single edge-triggered flip-flop before inputting the clock signal into a master stage of the single edge-triggered flip-flop, the single edge-triggered flip-flop's hold time may be reduced without negatively increasing a setup time of the single edge-triggered flip-flop.

Abstract: A method and apparatus for adjusting clock skew involves sensing a temperature at a location on an integrated circuit. A temperature sensor indicates a temperature value of the location on the integrated circuit. The temperature value is monitored, and a tunable buffer is adjusted dependent on the monitoring. The tunable buffer is used to adjust clock skew.

Abstract: A method and apparatus adjusts a propagation delay through a receiver circuit. A transmission apparatus is arranged to generate a control signal where an impedance of a driver circuit is dependent on the control signal. A bias generator is operatively connected to the transmission apparatus and is dependent on the control signal. A receiver circuit is operatively connected to the bias generator where the bias generator is arranged to operatively adjust a propagation delay through the receiver circuit.

Abstract: A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses an aging independent reference circuit and a bias circuit to operatively adjust a bias generator such that transistor ‘aging’ effects that occur over the lifetime of an integrated circuit are compensated for or corrected.

Abstract: A charge pump is arranged to generate a current dependent on a phase difference between a first signal and a second signal. A reference circuit is operatively connected to the charge pump and arranged to adjust the charge pump so that the charge pump is independent of an aging effect.

Abstract: A method and apparatus for sensing an aging effect on an integrated circuit using a sensor disposed on the integrated circuit and arranged to generate an output dependent on a condition of an element within the sensor. A processor operatively connected to the sensor is arranged to indicate a code dependent the output.

Abstract: A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.

Abstract: A technique that uses active shields to reduce clock skew is provided. The technique uses a shield wire for shielding the signal wire, a driver stage for driving a leading clock signal on the shielding wire, and a signal wire buffer for driving a lagging clock signal on the signal wire, where the leading clock signal is driven onto the first shield wire a phase difference before the lagging clock signal is driven onto the signal wire.

Abstract: An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.

Abstract: A method and apparatus to determine skew of an on-chip signal without physical probing of the on-chip signal on the chip is provided. The method and apparatus use an externally generated reference signal that is distributed to one or more on-chip samplers that input the on-chip signal. Then, by modulating the externally generated reference signal, transitions of the on-chip signal can be detected at the one or more on-chip samplers so that the skew of the on-chip signal can be determined.

Abstract: A technique that uses active shields to reduce clock skew is provided. The technique uses a shield wire for shielding the signal wire, a driver stage for driving a leading clock signal on the shielding wire, and a signal wire buffer for driving a lagging clock signal on the signal wire, where the leading clock signal is driven onto the first shield wire a phase difference before the lagging clock signal is driven onto the signal wire.

Abstract: A method for reducing voltage variation in the power supply system of a phase locked loop has been developed. The method includes powering up a phase locked loop and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the phase locked loop, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: An apparatus for reducing power supply noise in the power supply system of a clock driver has been developed. The apparatus includes a clock driver with a power supply system connected to the clock driver and a shunting resistor connected across the power supply system in parallel with the clock driver.

Abstract: A method for verifying on-chip decoupling capacitance by formulating and solving a linear problem. Further, a software tool for determining decoupling capacitance on a computer chip using a linear problem. Further, a method for designing an integrated circuit such that there is enough decoupling capacitance on the integrated circuit.

Abstract: A method and apparatus for dividing a signal's frequency by a non-integer value is provided. Further, a method and apparatus for dividing a signal's frequency by a non-integer value by counting phases of the signal is provided.

Abstract: A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the delay locked loop. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated.

Abstract: A method and apparatus for post-fabrication adjustment of a phased locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the phase locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the phased locked loop allows a designer to achieve a desired phase locked loop operating characteristic after fabrication of the adjustable phase locked loop.

Abstract: A method and apparatus for post-fabrication adjustment of a phase locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the phase locked loop. The capacitor connects to a control voltage of the phase locked loop. Such control of the leakage current in the phase locked loop allows a designer to achieve a desired phase locked loop operating characteristic after the phase locked loop has been fabricated.

Abstract: A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after fabrication of the adjustable delay locked loop.