Patents by Inventor Pradeep R. Trivedi

Pradeep R. Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reducing PECL voltage variation
    Patent number: 6556041
    Abstract: A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: April 29, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude R. Gauthier, Pradeep R. Trivedi, Dean Liu, Brian Amick
  • Deskewing global clock skew using localized DLLs
    Publication number: 20030071669
    Abstract: A method for reducing global clock skew by referencing a first point on an integrated circuit to which to align other points on the integrated circuit is provided. Further, an integrated circuit that has localized DLLs having adjustable buffers that selectively drive a signal on a clock grid is provided. Further, a technique for using a local DLL, one or more phase detectors, and one or more DLLs connected to portions of a clock grid to reduce clock skew is provided.
    Type: Application
    Filed: October 11, 2001
    Publication date: April 17, 2003
    Inventors: Dean Liu, Tyler J. Thorp, Pradeep R. Trivedi, Gin S. Yee, Claude R. Gauthier
  • REDUCING PECL VOLTAGE VARIATION
    Publication number: 20030071650
    Abstract: A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.
    Type: Application
    Filed: October 16, 2001
    Publication date: April 17, 2003
    Inventors: Claude R. Gauthier, Pradeep R. Trivedi, Dean Liu, Brian Amick
  • Apparatus for reducing the supply noise near large clock drivers
    Publication number: 20030035310
    Abstract: An apparatus for reducing power supply noise in the power supply system of a clock driver has been developed. The apparatus includes a clock driver with a power supply system connected to the clock driver and a shunting resistor connected across the power supply system in parallel with the clock driver.
    Type: Application
    Filed: August 14, 2001
    Publication date: February 20, 2003
    Inventors: Claude R. Gauthier, Brian W. Amick, Tyler J. Thorp, Pradeep R. Trivedi, Dean Liu
  • Reducing clock skew by power supply isolation
    Publication number: 20030037271
    Abstract: A method and apparatus for reducing clock skew by isolating power distribution to a clock tree from chip logic is provided. Further, the present invention uses separate leads through a circuit board to distribute power from a power supply to a clock tree and a chip logic.
    Type: Application
    Filed: August 15, 2001
    Publication date: February 20, 2003
    Inventors: Dean Liu, Tyler J. Thorp, Pradeep R. Trivedi, Gin S. Yee
  • Measuring skew using on-chip sampling
    Publication number: 20030036862
    Abstract: A method and apparatus to determine skew of an on-chip signal without physical probing of the on-chip signal on the chip is provided. The method and apparatus use an externally generated reference signal that is distributed to one or more on-chip samplers that input the on-chip signal. Then, by modulating the externally generated reference signal, transitions of the on-chip signal can be detected at the one or more on-chip samplers so that the skew of the on-chip signal can be determined.
    Type: Application
    Filed: August 14, 2001
    Publication date: February 20, 2003
    Inventors: Dean Liu, Gin S. Yee, Tyler J. Thorp, Pradeep R. Trivedi
  • Verifying on-chip decoupling capacitance
    Publication number: 20030034783
    Abstract: A method for verifying on-chip decoupling capacitance by formulating and solving a linear problem is provided. Further, a software tool for determining decoupling capacitance on a computer chip using a linear problem is provided. Further, a method for designing an integrated circuit such that there is enough decoupling capacitance on the integrated circuit is provided.
    Type: Application
    Filed: August 17, 2001
    Publication date: February 20, 2003
    Inventors: Tyler J. Thorp, Pradeep R. Trivedi, Dean Liu
  • Non-integer division of frequency
    Publication number: 20030034810
    Abstract: A method and apparatus for dividing a signal's frequency by a non-integer value is provided. Further, a method and apparatus for dividing a signal's frequency by a non-integer value by counting phases of the signal is provided.
    Type: Application
    Filed: August 14, 2001
    Publication date: February 20, 2003
    Inventors: Pradeep R. Trivedi, Tyler J. Thorp, Dean Liu
  • Method for reducing peak to peak jitter in a dual-loop delay locked loop
    Patent number: 6501328
    Abstract: A method for reducing power supply noise in the power supply system of a delay locked loop has been developed. The method includes powering up a delay locked loop and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the delay locked loop.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: December 31, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude R. Gauthier, Brian W. Amick, Tyler J. Thorp, Dean Liu, Pradeep R. Trivedi
  • Method for reducing supply noise near an on-die thermal sensor
    Patent number: 6476663
    Abstract: A method for reducing power supply noise in the power supply system of a thermal sensor has been developed. The method includes powering up a thermal sensor and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the thermal sensor.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: November 5, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude R. Gauthier, Brian W. Amick, Tyler J. Thorp, Dean Liu, Pradeep R. Trivedi