Patents by Inventor Pradeep Trivedi

Pradeep Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6664828
    Abstract: A post-silicon technique for adjusting a current of a charge pump in a phase locked loop is provided. The technique involves use of an adjustment circuit operatively connected to the charge pump, where the adjustment circuit is controllable to facilitate an internal biasing of the charge pump. Such control of the charge pump current in a phase locked loop allows a designer to achieve desired PLL performance characteristics after the PLL has been fabricated.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: December 16, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude Gauthier, Brian Amick, Pradeep Trivedi, Dean Liu
  • Patent number: 6664831
    Abstract: A charge pump design that facilitates post-fabrication control of delay locked loop charge pump current is provided. The charge pump includes an adjustment device responsive to user controlled signals that are varied to achieve a desired amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired DLL performance characteristic after the DLL has been fabricated.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: December 16, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude Gauthier, Brian Amick, Dean Liu, Pradeep Trivedi
  • Publication number: 20030223301
    Abstract: A modulation circuit arranged to modulate a first voltage from a first power supply grid to produce a desired second voltage not greater than the first voltage on a second power supply grid is provided. A digital register is operatively connected to the modulation circuit to determine the desired second voltage on the second power supply grid. Furthermore, the digital register maintains a value representative of an activity level or an anticipated activity level of a circuit connected to the second power supply grid. The modulation circuit maintains the desired second voltage for the circuit connected to the second power supply grid by transferring charge between capacitances.
    Type: Application
    Filed: May 28, 2002
    Publication date: December 4, 2003
    Inventors: Pradeep Trivedi, Sudhakar Bobba
  • Patent number: 6658629
    Abstract: A technique for optimizing decoupling capacitance on an integrated circuit while meeting leakage power constraints of the integrated circuit is provided. The technique involves the formulation of a linear optimization problem using physical characteristics and constraints of the integrated circuit, where a linear solution to the linear optimization problem yields an optimal decoupling capacitance presence on the integrated circuit.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: December 2, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Sudhakar Bobba, Pradeep Trivedi, Tyler Thorp
  • Publication number: 20030215042
    Abstract: An adjustment and calibration system for post-fabrication treatment of a phase locked loop input receiver is provided. The adjustment and calibration system includes at least one adjustment circuit, to which the phase locked loop input receiver is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 20, 2003
    Inventors: Claude R. Gauthier, Brian W. Amick, Pradeep Trivedi, Dean Liu
  • Publication number: 20030214998
    Abstract: An adjustment and calibration system for post-fabrication treatment of an on-chip temperature sensor is provided. As explained in detail below, the adjustment and calibration system includes at least one adjustment circuit, to which the on-chip temperature sensor is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 20, 2003
    Inventors: Claude Gauthier, Brian Amick, Spencer Gold, Pradeep Trivedi, Lynn Ooi
  • Publication number: 20030214333
    Abstract: An adjustment and calibration system for post-fabrication treatment of a phase locked loop charge pump is provided. The adjustment and calibration system includes at least one adjustment circuit, to which a phase locked loop charge pump output is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 20, 2003
    Inventors: Claude R. Gauthier, Brian W. Amick, Dean Liu, Pradeep Trivedi
  • Publication number: 20030215041
    Abstract: A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 20, 2003
    Inventors: Claude R. Gauthier, Brian W. Amick, Dean Liu, Pradeep Trivedi
  • Publication number: 20030214280
    Abstract: A calibration and adjustment system for post-fabrication control of a delay locked loop charge pump current is provided. The calibration and adjustment system includes an adjustment device that varies an amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the charge pump current may be stored and subsequently read to adjust the delay locked loop.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 20, 2003
    Inventors: Claude R. Gauthier, Brian W. Amick, Pradeep Trivedi, Dean Liu
  • Publication number: 20030214362
    Abstract: A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the phase locked loop.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 20, 2003
    Inventors: Claude R. Gauthier, Brian W. Amick, Pradeep Trivedi, Dean Liu
  • Publication number: 20030212965
    Abstract: A technique for optimizing decoupling capacitance on an integrated circuit while meeting leakage power constraints of the integrated circuit is provided. The technique involves the formulation of a linear optimization problem using physical characteristics and constraints of the integrated circuit, where a linear solution to the linear optimization problem yields an optimal decoupling capacitance presence on the integrated circuit.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 13, 2003
    Inventors: Sudhakar Bobba, Pradeep Trivedi, Tyler Thorp
  • Patent number: 6646473
    Abstract: A dynamic circuit capable of operating in a normal power consumption mode and at least one reduced power consumption mode is provided. The dynamic circuit is operatively connected to a normal supply voltage and a reduced supply voltage, and is capable of operating at either the normal supply voltage and a normal frequency or at the reduced supply voltage and a reduced frequency. By using such a dynamic circuit, power consumption may be selectively controlled in order to reduce unnecessary power consumption.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: November 11, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Pradeep Trivedi, Sudhakar Bobba
  • Patent number: 6646472
    Abstract: A technique for reducing the power consumed by a clock driver circuit involves selecting between a first power supply path and a second power supply path in response to a power reduction signal. A driver circuit drives an output clock signal from the selected one of the first power supply path and the second power supply path. By reducing the voltage on one of the first power supply path and the second power supply path, the power consumed by the clock driver circuit may be selectively reduced.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: November 11, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Pradeep Trivedi, Sudhakar Bobba
  • Patent number: 6642756
    Abstract: A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: November 4, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Gin Yee, Sudhakar Bobba, Lynn Ooi, Pradeep Trivedi
  • Publication number: 20030201841
    Abstract: A phase locked loop that includes a receiver that is adjustable to substantially match delay of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry are responsive to one or more bias signals that are adjustable using one or more adjustment circuits that are operatively connected to the receiver. The control of the one or more bias signals via the one or more adjustment circuits facilitates the generation of substantially delay matched system and feedback clocks.
    Type: Application
    Filed: April 24, 2002
    Publication date: October 30, 2003
    Inventors: Claude Gauthier, Brian Amick, Pradeep Trivedi, Dean Liu
  • Publication number: 20030201809
    Abstract: A charge pump design that facilitates post-fabrication control of delay locked loop charge pump current is provided. The charge pump includes an adjustment device responsive to user controlled signals that are varied to achieve a desired amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired DLL performance characteristic after the DLL has been fabricated.
    Type: Application
    Filed: April 24, 2002
    Publication date: October 30, 2003
    Inventors: Claude Gauthier, Brian Amick, Dean Liu, Pradeep Trivedi
  • Publication number: 20030204358
    Abstract: A temperature sensor adapted to produce a temperature-independent voltage and temperature-dependent voltage dependent on an internal control signal, generated within the temperature sensor, adjustable by an adjustment circuit operatively connected to the temperature sensor is provided. The adjustment circuit is controllable to adjust the internal control signal in order to modify an operating characteristic of the temperature sensor.
    Type: Application
    Filed: April 24, 2002
    Publication date: October 30, 2003
    Inventors: Claude Gauthier, Brian Amick, Spencer Gold, Pradeep Trivedi, Lynn Ooi
  • Publication number: 20030201808
    Abstract: A post-silicon technique for adjusting a current of a charge pump in a phase locked loop is provided. The technique involves use of an adjustment circuit operatively connected to the charge pump, where the adjustment circuit is controllable to facilitate an internal biasing of the charge pump. Such control of the charge pump current in a phase locked loop allows a designer to achieve desired PLL performance characteristics after the PLL has been fabricated.
    Type: Application
    Filed: April 24, 2002
    Publication date: October 30, 2003
    Inventors: Claude Gauthier, Brian Amick, Pradeep Trivedi, Dean Liu
  • Patent number: 6640331
    Abstract: A decoupling capacitor assignment technique that increases decoupling capacitance without violating a leakage power constraint of an integrated circuit is provided. The decoupling capacitor assignment technique selectively replaces decoupling capacitors associated with high driver decoupling capacitance need to available decoupling capacitance ratios with thin-oxide decoupling capacitors such that decoupling capacitance is increased and the leakage power constraint is met.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: October 28, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Pradeep Trivedi, Sudhakar Bobba, Tyler Thorp
  • Publication number: 20030193375
    Abstract: A phase locked loop that includes a receiver circuit for matching delays of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver circuit employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry control the generation of substantially delay matched system and feedback clocks.
    Type: Application
    Filed: April 12, 2002
    Publication date: October 16, 2003
    Inventors: Claude Gauthier, Pradeep Trivedi, Brian Amick