Patents by Inventor Pradip Bose

Pradip Bose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240013050
    Abstract: An example system includes a processor to prune a machine learning model based on an importance of neurons or weights. The processor is to further permute and pack remaining neurons or weights of the pruned machine learning model to reduce an amount of ciphertext computation under a selected constraint.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 11, 2024
    Inventors: Subhankar PAL, Alper BUYUKTOSUNOGLU, Ehud AHARONI, Nir DRUCKER, Omri SOCEANU, Hayim SHAUL, Kanthi SARPATWAR, Roman VACULIN, Moran BARUCH, Pradip BOSE
  • Patent number: 11810340
    Abstract: A system includes a determination component that determines output for successively larger neural networks of a set; and a consensus component that determines consensus between a first neural network and a second neural network of the set. A linear chain of increasingly complex neural networks trained on progressively larger inputs is utilized (e.g., increasingly complex neural networks is generally representative of increased accuracy). Outputs of progressively networks are computed until a consensus point is reached—where two or more successive large networks yield a same inference output. At such point of consensus the larger neural network of the set reaching consensus can be deemed appropriately sized (or of sufficient complexity) for a classification task at hand.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Swagath Venkataramani
  • Publication number: 20230281518
    Abstract: Second machine learning models trained using respective second data sets can be received. The second machine learning models can be run using a first data set used in training a first machine learning model, where the second machine learning models produce respective outputs. Scores associated with the second machine learning models can be determined by comparing the respective outputs with ground truth associated with the first data set. Based on the scores associated with the second machine learning models, whether the first data set is to be discarded or kept can be determined for training the first machine learning model.
    Type: Application
    Filed: March 4, 2022
    Publication date: September 7, 2023
    Inventors: Dinesh C. Verma, Supriyo Chakraborty, Shiqiang Wang, Augusto Vega, Hazar Yueksel, Ashish Verma, Pradip Bose, Jayaram Kallapalayam Radhakrishnan
  • Patent number: 11740933
    Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: August 29, 2023
    Assignee: International Business Machines Corporation
    Inventors: Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Pradip Bose, Robert Matthew Senger, Aporva Amarnath
  • Patent number: 11734084
    Abstract: Systems, computer-implemented methods and/or computer program products that facilitate management of resources are provided. In one embodiment, a computer-implemented method comprises: employing, by a system operatively coupled to a processor, at least one model to predict respective token needs by a set of processing elements during execution of a workload; and exchanging, by the system, one or more tokens between a subset of the processing elements as a function of the predicted token needs.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: August 22, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Augusto Vega, Alper Buyuktosunoglu, Pradip Bose, Vaidyanathan Srinivasan, Ranjal Gautham Shenoy
  • Patent number: 11720469
    Abstract: A computer-implemented method, a computer system and a computer program product customize generation and application of stress test conditions in a processor core. The method includes receiving a workload at the processor core, where the workload includes a plurality of instructions and the processor core comprises a plurality of macros. The method also includes obtaining macro performance data for each macro in the plurality of macros from the processor core. The method further includes determining a switching activity level for each macro in the plurality of macros when each instruction in the plurality of instructions is run based on the macro performance data. Lastly, the method includes generating a stressmark comprising the plurality of instructions in the workload, where the stressmark is associated with a macro in the plurality of macros when the switching activity level for the macro is above a minimum threshold.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: August 8, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik V Swaminathan, Ramon Bertran Monfort, Alper Buyuktosunoglu, Pradip Bose
  • Patent number: 11704155
    Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: July 18, 2023
    Assignee: International Business Machine Corporation
    Inventors: Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Pradip Bose, Robert Matthew Senger, Aporva Amarnath
  • Publication number: 20230222279
    Abstract: Embodiments for providing enhanced location-aware protection of latches in a computing environment are provided. One or more latches are combined in one or more of a plurality of bounding boxes on a two-dimensional circuit design layout based on one or more rules. A location-aware interleaving of error correction codes (“ECC”) and burst error correction codes may be selectively applied to one or more latches in those of the plurality of bounding boxes, where multiple bit errors are corrected.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik V SWAMINATHAN, Alper BUYUKTOSUNOGLU, Pradip BOSE, Bulent ABALI
  • Patent number: 11693728
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: July 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
  • Patent number: 11630152
    Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: April 18, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
  • Patent number: 11620207
    Abstract: Various embodiments are provided for load balancing of machine learning operations in a computing environment by a processor. One or more machine learning operations performing inference or training operations may by dynamically balanced between one or more edge computing devices in a wireless communication network and a cloud computing system for increasing performance of a selected metric.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Augusto Vega, Alper Buyuktosunoglu, Pradip Bose
  • Patent number: 11599795
    Abstract: An N modular redundancy method, system, and computer program product include a computer-implemented N modular redundancy method for neural networks, the method including selectively replicating the neural network by employing one of checker neural networks and selective N modular redundancy (N-MR) applied only to critical computations.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: March 7, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V Swaminathan, Augusto Vega, Swagath Venkataramani
  • Patent number: 11586478
    Abstract: Systems, computer-implemented methods and/or computer program products that facilitate management of resources are provided. In one embodiment, a computer-implemented method comprises: employing, by a system operatively coupled to a processor, at least one model to predict respective token needs by a set of processing elements during execution of a workload; and exchanging, by the system, one or more tokens between a subset of the processing elements as a function of the predicted token needs.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: February 21, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Augusto Vega, Alper Buyuktosunoglu, Pradip Bose, Vaidyanathan Srinivasan, Ranjal Gautham Shenoy
  • Patent number: 11561595
    Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: January 24, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Phillip John Restle, Christos Vezyrtzis
  • Publication number: 20230012710
    Abstract: Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 19, 2023
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aporva AMARNATH, Augusto VEGA, Alper BUYUKTOSUNOGLU, Hubertus FRANKE, John-David WELLMAN, Pradip BOSE
  • Publication number: 20220343218
    Abstract: Embodiments relate to an input-encoding technique in conjunction with federation. Participating entities are arranged in a collaborative relationship. Each participating entity trains a machine learning model with an encoder on a training data set. The performance of each of the models is measured and at least one of the models is selectively identified based on the measured performance. An encoder of the selectively identified machine learning model is shared with each of the participating entities. The shared encoder is configured to be applied by the participating entities to train the first and second machine learning models, which are configured to be merged and shared in the federated learning environment.
    Type: Application
    Filed: April 26, 2021
    Publication date: October 27, 2022
    Applicant: International Business Machines Corporation
    Inventors: Hazar Yueksel, Brian E. D. Kingsbury, Kush Raj Varshney, Pradip Bose, Dinesh C. Verma, Shiqiang Wang, Augusto Vega, ASHISH VERMA, SUPRIYO CHAKRABORTY
  • Patent number: 11475274
    Abstract: A computer-implemented method optimizes a neural network. One or more processors define layers in a neural network based on neuron locations relative to incoming initial inputs and original outgoing final outputs of the neural network, where a first defined layer is closer to the incoming initial inputs than a second defined layer, and where the second defined layer is closer to the original outgoing final outputs than the first defined layer. The processor(s) define parameter criticalities for parameter weights stored in a memory used by the neural network, and associate defined layers in the neural network with different memory banks based on the parameter criticalities for the parameter weights. The processor(s) store parameter weights used by neurons in the first defined layer in the first memory bank and parameter weights used by neurons in the second defined layer in the second memory bank.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Augusto J. Vega
  • Patent number: 11360772
    Abstract: Embodiments for implementing optimized accelerators in a computing environment are provided. Selected instruction sequence code blocks derived from one or more application workloads may be consolidated together to activate one or more accelerators subject to one or more constraints and projections.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 14, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alper Buyuktosunoglu, David Trilla Rodriguez, John-David Wellman, Pradip Bose
  • Publication number: 20220179465
    Abstract: Techniques for inducing non-uniform cooling are described. According to an embodiment, a system is provided. The system can comprise at least one processor device that executes components stored in a memory, wherein the components comprise: a flow control device that distributes coolant to a location of the at least one processor device; and a sensor controller component that detects a location of a thermal anomaly of the at least one processor device. The components can also comprise a cooling controller component that adjusts the flow control device to direct the coolant to the location of the thermal anomaly.
    Type: Application
    Filed: January 3, 2020
    Publication date: June 9, 2022
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Timothy Joseph Chainer, Pritish Ranjan Parida, Augusto Javier Vega
  • Publication number: 20220164250
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 26, 2022
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel