Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.

Abstract: Methods and systems for executing an application includes executing an epoch of the application using a predicted minimum operational voltage that is based on a previous epoch of the application if the application is in a stable phase and using a nominal safe voltage if the application is in an unstable phase.

Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.

Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.

Abstract: Methods and systems for executing an application includes predicting a minimum operational voltage for a next epoch of an application based on performance counters collected in a previous epoch of the application. The next epoch of the application is executed using the predicted minimum operational voltage if the application is in a stable phase and using a nominal safe voltage if the application is in an unstable phase.

Abstract: A computer-implemented method optimizes a neural network. One or more processors define layers in a neural network based on neuron locations relative to incoming initial inputs and original outgoing final outputs of the neural network, where a first defined layer is closer to the incoming initial inputs than a second defined layer, and where the second defined layer is closer to the original outgoing final outputs than the first defined layer. The processor(s) define parameter criticalities for parameter weights stored in a memory used by the neural network, and associate defined layers in the neural network with different memory banks based on the parameter criticalities for the parameter weights. The processor(s) store parameter weights used by neurons in the first defined layer in the first memory bank and parameter weights used by neurons in the second defined layer in the second memory bank.

Abstract: Embodiments of the present invention include a system, computer-implemented method, and a computer program product. A non-limiting example of the method includes a processor utilizing a model having a plurality of parameters. The processor compares a current value of a model parameter to a prior value of the model parameter. Based at least in part on comparing the current value of the model parameter to the prior value of the model parameter, a determination is made that the model being utilized by the processor has changed. The current value of the model parameter is transmitted by the processor.

Abstract: A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures.

Abstract: A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures.

Abstract: One aspect is an analysis system that includes a processor operably coupled to a memory and configured to perform a method. The method includes defining a set of workloads for a targeted multi-core computer system based on a plurality of metrics of interest to profile. A plurality of workload-to-core mappings is generated for the workloads on the targeted multi-core computer system. The workloads run on the targeted multi-core computer system based on the workload-to-core mappings to produce a mapping of the workloads to the metrics of interest as experimental data. A statistical analysis is applied on the experimental data to define a plurality of metric profiles for the targeted multi-core computer system.

Abstract: A computer-implemented method includes determining, by a first base station, that the first base station is overloaded with connections from mobile devices. Responsive to the first base station being overloaded, a status update may be received, by the first base station, from each of a plurality of base stations, where each base station is configured to provide connections to a plurality of mobile devices. Responsive to the first base station being overloaded, a second base station may be selected, by a computer processor of the first base station, from among the plurality of base stations. Responsive to the first base station being overloaded, the second base station may be instructed, by the first base station, to relocate from a first position to a new position closer to the first base station. The plurality of base stations automatically relocate to load-balance connections from the plurality of mobile devices.

Abstract: A computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to cause the processor to perform a method that includes determining, by a first base station, that the first base station is overloaded with connections from mobile devices. Responsive to the first base station being overloaded, a status update may be received, by the first base station, from each of a plurality of base stations. A second base station may be selected, by the first base station, from among the plurality of base stations. Responsive to the first base station being overloaded, the second base station may be instructed, by the first base station, to relocate from a first position to a new position closer to the first base station. The plurality of base stations automatically relocate to load-balance connections from the plurality of mobile devices.

Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted complex-instruction set computer (CISC) processor to generate an instruction set profile for each CISC architectural instruction variant of the instruction set architecture. A combination of instruction sequences for the targeted CISC processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted CISC processor. Performance of the targeted CISC processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. The targeted CISC processor is stress tested based on executing at least one of the instruction sequences identified as most closely aligning with the desired stressmark type.

Abstract: Embodiments relate to clustering execution in a processing system. An aspect includes accessing a control flow graph that defines a data dependency and an execution sequence of a plurality of tasks of an application that executes on a plurality of system components. The execution sequence of the tasks in the control flow graph is modified as a clustered control flow graph that clusters active and idle phases of a system component while maintaining the data dependency. The clustered control flow graph is sent to an operating system, where the operating system utilizes the clustered control flow graph for scheduling the tasks.

Abstract: Techniques for inducing non-uniform cooling are described. According to an embodiment, a system is provided. The system can comprise at least one processor device that executes components stored in a memory, wherein the components comprise: a flow control device that distributes coolant to a location of the at least one processor device; and a sensor controller component that detects a location of a thermal anomaly of the at least one processor device. The components can also comprise a cooling controller component that adjusts the flow control device to direct the coolant to the location of the thermal anomaly.

Abstract: Embodiments relate to clustering execution in a processing system. An aspect includes accessing a control flow graph that defines a data dependency and an execution sequence of a plurality of tasks of an application that executes on a plurality of system components. The execution sequence of the tasks in the control flow graph is modified as a clustered control flow graph that clusters active and idle phases of a system component while maintaining the data dependency. The clustered control flow graph is sent to an operating system, where the operating system utilizes the clustered control flow graph for scheduling the tasks.

Abstract: Techniques for inducing heterogeneous microprocessor behavior using non-uniform cooling are described. According to an embodiment, a device is provided that comprises an IC chip comprising a plurality of cores and a cooling apparatus coupled to the integrated chip that cools the integrated chip in association with electrical operation of the plurality of cores. The cooling apparatus cools a first core of the plurality of cores to a lower temperature than a second core of the plurality of cores. In various embodiments, the cooling apparatus comprises a plurality of channels embedded within the integrated chip and the cooling apparatus cools the integrated chip via flow of liquid coolant through the plurality of channels.

Abstract: Techniques for decoupling cognitive model training from execution of the cognitive model are provided. In one example, a computer program product is provided that determines cognitive data based on context data and a model of interpreting the context data. The cognitive data can comprise prediction data that represents a prediction relating to a state of an environment. The context data and the cognitive data can be transmitted to a server, and an updated model can be received in response.

Abstract: Techniques for implementing a safety protocol are provided. In one example, a system is provided that can execute a machine-learned model to determine cognitive data representing a prediction about a state of an environment and an action to be performed in response to the prediction. The system can determine that a connection with a remote device is unavailable, and in response activate a safety protocol.

Abstract: An aspect includes pruning a design space when generating a maximum power stressmark. A multi-stage design space search process is performed. Each stage includes calculating a number of instructions per cycle (IPC) for each instruction sequence in a set of instruction sequences that place a power stress on a system under analysis, removing one or more of the instruction sequences having an IPC lower than a pruning threshold from the set, evaluating at least one power metric of the remaining instruction sequences in the set, removing one or more of the instruction sequences having at least one power metric evaluated outside of one or more pruning ranges from the set, and passing the remaining instruction sequences in the set to a next stage. A maximum power stressmark is generated based on the evaluating of the at least one power metric from a final stage.