Abstract: A computer monitors a memory system during operation. The computer detects a first number of errors in the memory system. The computer determines that the first number of errors is below an error level threshold. The computer lowers a first group of one or more memory parameters of the memory system by a first amount. After the lowering of one or more memory parameters by the first amount, the computer detects a second number of errors in the memory system. The computer determines that the second number of errors is above the error level threshold. The computer raises a second group of one or more memory parameters of the memory system by a second amount.

Abstract: Techniques for inducing non-uniform cooling are described. According to an embodiment, a system is provided. The system can comprise at least one processor device that executes components stored in a memory, wherein the components comprise: a flow control device that distributes coolant to a location of the at least one processor device; and a sensor controller component that detects a location of a thermal anomaly of the at least one processor device. The components can also comprise a cooling controller component that adjusts the flow control device to direct the coolant to the location of the thermal anomaly.

Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

Abstract: A central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays.

Abstract: In a first device in response to an event input, using a processor and a memory, a local classification and a local classification confidence score corresponding to the event input are computed. At the first device in response to a broadcast request, a remote classification and a remote classification confidence score corresponding to the event input are received, the remote classification and the remote classification confidence score being computed at a second device. At the first device, a consensus classification including the most frequent classification from a set of all received remote classifications and the local classification is formed, provided the number of classifications including the most frequent classification exceeds a threshold. In response to a consensus classification confidence score corresponding to the consensus classification exceeding a confidence threshold, a local classification model is updated.

Abstract: Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Abstract: A computer-implemented method includes determining, by a first base station, that the first base station is overloaded with connections from mobile devices. Responsive to the first base station being overloaded, a status update may be received, by the first base station, from each of a plurality of base stations, where each base station is configured to provide connections to a plurality of mobile devices. Responsive to the first base station being overloaded, a second base station may be selected, by a computer processor of the first base station, from among the plurality of base stations. Responsive to the first base station being overloaded, the second base station may be instructed, by the first base station, to relocate from a first position to a new position closer to the first base station. The plurality of base stations automatically relocate to load-balance connections from the plurality of mobile devices.

Abstract: Techniques for inducing heterogeneous microprocessor behavior using non-uniform cooling are described. According to an embodiment, a device is provided that comprises an IC chip comprising a plurality of cores and a cooling apparatus coupled to the integrated chip that cools the integrated chip in association with electrical operation of the plurality of cores. The cooling apparatus cools a first core of the plurality of cores to a lower temperature than a second core of the plurality of cores. In various embodiments, the cooling apparatus comprises a plurality of channels embedded within the integrated chip and the cooling apparatus cools the integrated chip via flow of liquid coolant through the plurality of channels.

Abstract: A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures.

Abstract: A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures.

Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.

Abstract: Techniques for inducing heterogeneous microprocessor behavior using non-uniform cooling are described. According to an embodiment, a device is provided that comprises an IC chip comprising a plurality of cores and a cooling apparatus coupled to the integrated chip that cools the integrated chip in association with electrical operation of the plurality of cores. The cooling apparatus cools a first core of the plurality of cores to a lower temperature than a second core of the plurality of cores. In various embodiments, the cooling apparatus comprises a plurality of channels embedded within the integrated chip and the cooling apparatus cools the integrated chip via flow of liquid coolant through the plurality of channels.

Abstract: A system includes a determination component that determines output for successively larger neural networks of a set; and a consensus component that determines consensus between a first neural network and a second neural network of the set. A linear chain of increasingly complex neural networks trained on progressively larger inputs is utilized (e.g., increasingly complex neural networks is generally representative of increased accuracy). Outputs of progressively networks are computed until a consensus point is reached—where two or more successive large networks yield a same inference output. At such point of consensus the larger neural network of the set reaching consensus can be deemed appropriately sized (or of sufficient complexity) for a classification task at hand.

Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.

Abstract: A computer monitors a memory system during operation. The computer detects a first number of errors in the memory system. The computer determines that the first number of errors is below an error level threshold. The computer lowers a first group of one or more memory parameters of the memory system by a first amount. After the lowering of one or more memory parameters by the first amount, the computer detects a second number of errors in the memory system. The computer determines that the second number of errors is above the error level threshold. The computer raises a second group of one or more memory parameters of the memory system by a second amount.

Abstract: An N modular redundancy method, system, and computer program product include a computer-implemented N modular redundancy method for neural networks, the method including selectively replicating the neural network by employing one of checker neural networks and selective N modular redundancy (N-MR) applied only to critical computations.

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

Abstract: A system and method for projecting reliability to manage system functions includes an activity module which determines activity in the system. A reliability module interacts with the activity module to determine a reliability measurement for the module in real-time based upon the activity and measured operational quantities of the system. A management module manages actions of the system based upon the reliability measurement input from the reliability module. This may be to provide corrective action, to reallocate resources, or increase reliability of the module.