Abstract: In a solar panel array, each solar panel in a series-connected string has a current source connected across its output terminals. The current source generates a programmable output current equal to the difference of the load current drawn from the panel and the current corresponding to the maximum power point (MPP) of the panel. As a result, each of the panels in the string is operated at its MPP. When the array contains multiple strings connected in parallel, a voltage source is additionally connected in series with each string. The voltage sources are programmable to generate corresponding output voltages to enable operation of each panel in each of the multiple strings at its MPP. Respective control blocks providing the current sources and voltage sources automatically determine the MPP of the corresponding panels. In an embodiment, the control blocks are implemented as DC-DC converters in conjunction with measurement and communication units.

Abstract: An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.

Abstract: A circuit for reducing flicker noise includes a first current source coupled to an input current. The circuit includes current minors to generate output currents in response to the input current. The output currents include the flicker noise. In addition, the circuit includes a chopping circuit to reduce the flicker noise from each of the output currents.

Abstract: A voltage regulator includes an amplifier, a first buffer and a second buffer. The amplifier is designed to generate an error voltage between a reference voltage and a voltage at an output node of the voltage regulator. The first buffer is coupled to receive the amplified error voltage and, in response, to drive a first pass transistor. The first buffer includes a non-linear resistance element. The resistance of the non-linear resistance element varies non-linearly with a load current drawn from the output node. The second buffer is coupled to receive the amplified error voltage, and in response, to drive a second pass transistor. The second buffer includes a linear resistance element. The resistance of the linear element is a constant. The use of the non-linear resistance element enables reduction in power consumption in the voltage regulator.

Abstract: A system for generating electric power includes a first DC source, a second DC source and a shared optimizer. The first DC source provides a first voltage across a first node and a second node, while the second DC source provides a second voltage across the second node and a third node. The shared optimizer is designed to provide a first programmable current source between the first node and the second node as well as a second programmable current source between the second node and the third node. In an embodiment, the first and second DC sources are solar panels, and the optimizer includes a DC-DC converter, which operates to maximize power output of the solar panels. The use of a single (shared) optimizer may obviate the need for separate optimizers for each solar panel, and thereby reduce system cost.

Abstract: In a solar panel array that includes a string of series-connected panels, the load current flowing through the string is measured. The peak current (Ipp) of a panel in the string is determined. A current equal to the difference of the load current and the peak current (Ipp) is generated in a current source connected across the output terminals of the panel. The panel is thereby operated at its maximum power point (MPP). To determine the peak current (Ipp) of the panel, the magnitude of current flowing through the panel is iteratively changed and the corresponding power generated by the panel is computed. The change in the current through the panel and the measurement of the corresponding power are repeated until a maximum power is determined as being generated by the panel. The maximum power corresponds to the maximum power point (MPP) and the peak current (Ipp) of the panel.

Abstract: A transient recovery circuit for switching devices. The transient recovery circuit includes a detecting circuit for detecting a rapid transient in an output voltage of a switching device by detecting a rate of the output voltage transient; an auxiliary controlling circuit in a feedback loop of the switching device for correcting the output voltage by changing a bandwidth of the feedback loop if the rapid transient is detected; and an initializing circuit for initializing the feedback loop to expected operating points in a continuous conduction mode after correcting the output voltage.

Abstract: A voltage regulator includes an amplifier, a first buffer and a second buffer. The amplifier is designed to generate an error voltage between a reference voltage and a voltage at an output node of the voltage regulator. The first buffer is coupled to receive the amplified error voltage and, in response, to drive a first pass transistor. The first buffer includes a non-linear resistance element. The resistance of the non-linear resistance element varies non-linearly with a load current drawn from the output node. The second buffer is coupled to receive the amplified error voltage, and in response, to drive a second pass transistor. The second buffer includes a linear resistance element. The resistance of the linear element is a constant. The use of the non-linear resistance element enables reduction in power consumption in the voltage regulator.

Abstract: An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.

Abstract: A transient recovery circuit for switching devices. The transient recovery circuit includes a detecting circuit for detecting a rapid transient in an output voltage of a switching device by detecting a rate of the output voltage transient; an auxiliary controlling circuit in a feedback loop of the switching device for correcting the output voltage by changing a bandwidth of the feedback loop if the rapid transient is detected; and an initializing circuit for initializing the feedback loop to expected operating points in a continuous conduction mode after correcting the output voltage.

Abstract: A transient recovery circuit for switching devices. The transient recovery circuit includes a detecting circuit for detecting a rapid transient in an output voltage of a switching device by detecting a rate of the output voltage transient; an auxiliary controlling circuit in a feedback loop of the switching device for correcting the output voltage by changing a bandwidth of the feedback loop if the rapid transient is detected; and an initializing circuit for initializing the feedback loop to expected operating points in a continuous conduction mode after correcting the output voltage.

Abstract: Efficient switch cascode architecture for switching devices, such as switching regulators. The cascode architecture includes a switching stage responsive to an external driver signal for switching transitions, and a bias generator operative to bias the cascode transistor of the switching stage to protect the switching stage from damage during the switching transitions.

Abstract: In a solar panel array that includes a string of series-connected panels, the load current flowing through the string is measured. The peak current (Ipp) of a panel in the string is determined. A current equal to the difference of the load current and the peak current (Ipp) is generated in a current source connected across the output terminals of the panel. The panel is thereby operated at its maximum power point (MPP). To determine the peak current (Ipp) of the panel, the magnitude of current flowing through the panel is iteratively changed and the corresponding power generated by the panel is computed. The change in the current through the panel and the measurement of the corresponding power are repeated until a maximum power is determined as being generated by the panel. The maximum power corresponds to the maximum power point (MPP) and the peak current (Ipp) of the panel.

Abstract: In a solar panel array, each solar panel in a series-connected string has a current source connected across its output terminals. The current source generates a programmable output current equal to the difference of the load current drawn from the panel and the current corresponding to the maximum power point (MPP) of the panel. As a result, each of the panels in the string is operated at its MPP. When the array contains multiple strings connected in parallel, a voltage source is additionally connected in series with each string. The voltage sources are programmable to generate corresponding output voltages to enable operation of each panel in each of the multiple strings at its MPP. Respective control blocks providing the current sources and voltage sources automatically determine the MPP of the corresponding panels. In an embodiment, the control blocks are implemented as DC-DC converters in conjunction with measurement and communication units.

Abstract: A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.

Abstract: Single inductor multiple output (SIMO) switching devices with efficient regulating circuits. The SIMO switching device includes a plurality of time division multiplexing (TDM) switches for switching current through an inductor of the SIMO switching device. The plurality of TDM switches produces a plurality of outputs. The SIMO switching device further includes an error calculation circuit operatively coupled to the plurality of outputs for determining a calculated error from the plurality of outputs; a time slot generation circuit for controlling the plurality of TDM switches according to the calculated error; and a pulse width modulation (PWM) control circuit operatively coupled to the time slot generation circuit for controlling a plurality of PWM switches of a switching stage of the SIMO switching device in a continuous conduction mode (CCM) of operation. The PWM switches are controlled according to the time slots generated by the time slot generation circuit.

Abstract: A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit.

Abstract: Efficient switch cascode architecture for switching devices, such as switching regulators. The cascode architecture includes a switching stage responsive to an external driver signal for switching transitions, and a bias generator operative to bias the cascode transistor of the switching stage to protect the switching stage from damage during the switching transitions.

Abstract: A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

Abstract: A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.