Abstract: A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit.

Abstract: Single inductor multiple output (SIMO) switching devices with efficient regulating circuits. The SIMO switching device includes a plurality of time division multiplexing (TDM) switches for switching current through an inductor of the SIMO switching device. The plurality of TDM switches produces a plurality of outputs. The SIMO switching device further includes an error calculation circuit operatively coupled to the plurality of outputs for determining a calculated error from the plurality of outputs; a time slot generation circuit for controlling the plurality of TDM switches according to the calculated error; and a pulse width modulation (PWM) control circuit operatively coupled to the time slot generation circuit for controlling a plurality of PWM switches of a switching stage of the SIMO switching device in a continuous conduction mode (CCM) of operation. The PWM switches are controlled according to the time slots generated by the time slot generation circuit.

Abstract: A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

Abstract: A transient recovery circuit for switching devices. The transient recovery circuit includes a detecting circuit for detecting a rapid transient in an output voltage of a switching device by detecting a rate of the output voltage transient; an auxiliary controlling circuit in a feedback loop of the switching device for correcting the output voltage by changing a bandwidth of the feedback loop if the rapid transient is detected; and an initializing circuit for initializing the feedback loop to expected operating points in a continuous conduction mode after correcting the output voltage.

Abstract: Methods and systems for designing a high resolution analog to digital converter (ADC) by eliminating the errors in the ADC stages. An error correction architecture and method eliminate the gain error and settling error of the residue amplifier in a pipelined ADC stage. A reference voltage error correction architecture and method eliminate the reference voltage error due to the sampling action in the ADC. The gain error correction method calculates the gain error using an error amplifier and eliminates the gain error at a later stage of the ADC. The reference voltage error correction method calculates the reference voltage error using an ideal reference voltage and corrects the error at a later stage of the ADC. Therefore, the constraints of gain and settling of the residue amplifier is significantly reduced.

Abstract: A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.

Abstract: Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes at least two control signals. One of the control signals is provided by a circuit that is susceptible to drift. This control signal is provided both to a systems or device under control, and to a detection circuit. The detection circuit is operable to detect a drift in the control signal. In addition, the detection circuit provides another control signal that varies as a function of the drift in the received control signal.

Abstract: A trans-impedance filter circuit provided according to an aspect of the present invention contains an operational amplifier, a first resistor, a first capacitor, a second resistor, and a second capacitor. The second capacitor is connected in parallel between the inverting input terminal and an output path of the operational amplifier. The second resistor is connected between the output terminal of the operational amplifier and a second node on a path connecting the input signal to the inverting input terminal. The first resistor is coupled between the first node and inverting input terminal of the operational amplifier. The first capacitor is coupled between the first node and Vss. Due to such connections, the filter circuit operates as a second order filter circuit, thereby providing a desired high level of filtering. Also, as the filter circuit is implemented with a single operational amplifier, the power and area requirements are reduced.

Abstract: Methods and systems for designing a high resolution ADC by eliminating the errors in the ADC stages. An error correction architecture and method of the embodiments of the invention eliminate the gain error and settling error of the residue amplifier in a pipelined ADC stage. A reference voltage error correction architecture and method of the embodiments of the invention eliminate the reference voltage error due to the sampling action in the ADC. The gain error correction method calculates the gain error using an error amplifier and eliminates the gain error at a later stage of the ADC. The reference voltage error correction method calculates the reference voltage error using an ideal reference voltage and corrects the error at a later stage of the ADC. The constraints of gain and settling of the residue amplifier is significantly reduced using the embodiments of the invention.

Abstract: A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.

Abstract: A method for reducing transmit echo in a DSL modem comprises selecting at least one cancellation device of a plurality of cancellation devices. An attenuation signal is generated using the selected cancellation device. At least a portion of transmit echo is removed from a receive signal using the attenuation signal.

Abstract: Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes at least two control signals. One of the control signals is provided by a circuit that is susceptible to drift. This control signal is provided both to a systems or device under control, and to a detection circuit. The detection circuit is operable to detect a drift in the control signal. In addition, the detection circuit provides another control signal that varies as a function of the drift in the received control signal.

Abstract: A receiver, implemented with low noise and low distortion, to process an input signal containing signals of interest and unwanted interference signal. In an embodiment, the receiver contains a mixer which generates an intermediate signal in the form of an electric current, and a filter which filters the unwanted interference signals from the intermediate signal. The intermediate signal is centered around a lower frequency compared to a carrier frequency of the input signal. Due to the current mode interface between the mixer and the filter circuit, low noise and low distortion may be attained.

Abstract: A low distortion filter circuit implementing variable gain amplification (VGA). An aspect of the present invention increases the degrees of freedom (number of components which can be independently programmed/changed to corresponding desired values) to achieve a desired combination of D.C. gain and filter characteristics (e.g., corner frequency, Q-factor, notch frequency, etc.). Such additional degrees of freedom are attained by including additional components in either on input block or a feedback block (implemented with reference to an operational amplifier), and by redesigning the other block using principles such as admittance concellation to remove the effects of such additional components. The blocks are designed such that a terminal of the programmable components is connected to a fixed/constant voltage (e.g., ground). Embodiments implementing bi-quad single amplifier with and without notch are disclosed.

Abstract: A low distortion filter circuit implementing variable gain amplification (VGA). An aspect of the present invention increases the degrees of freedom (number of components which can be independently programmed/changed to corresponding desired values) to achieve a desired combination of D.C. gain and filter characteristics (e.g., corner frequency, Q-factor, notch frequency, etc.). Such additional degrees of freedom are attained by including additional components in either an input block or a feedback block (implemented with reference to an operational amplifier), and by redesigning the other block using principles such as admittance cancellation to remove the effects of such additional components. The blocks are designed such that a terminal of the programmable components is connected to a fixed/constant voltage (e.g., ground). Embodiments implementing bi-quad single amplifier with and without notch are disclosed.

Abstract: An active filter circuit containing small capacitors. Due to the presence of such small capacitors, components such as PLL can potentially be integrated into integrated circuits. In an embodiment, the filter circuit is implemented by having a combination of a first capacitor and a first resistor connected in series providing the input signal to the input terminal of a operational amplifier, and a second resistor being connected in parallel to the combination. A second capacitor may be connected between the input and output terminals of the operational amplifier. The first capacitor may be chosen to be small by choosing the second resistor to be of a large resistance. Any noise introduced by such a large resistor may be attenuated by choosing the first resistor to be small.

Abstract: A method of providing an improved transfer function for a Discrete Multitone (DMT) type modulation transmitter with digital filtering after modulation followed by digital to analog converter and analog filtering is provided by sending a test signal to said transmitter and measuring the results of the test signal to determine the transfer function. The inverse of the transfer function that needs to be compensated is determined and the inverse of transfer function to be compensated is truncated to the region of interest (H2). The desired band split component of pre-compensation filter is designed (H3). The desired target frequency response of the pre-compensation filter is determined by H4=H2*H3 where H4 is the multiplication of H2 and H3 Given the target frequency response in H4 Hermetian symmetry is imposed on the frequency response. The inverse Fourier transform (IFFT) is taken to generate a time domain filter, h5. The characteristic of this filter is added at the digital filtering after modulation.

Abstract: A trans-impedance filter circuit provided according to an aspect of the present invention contains an operational amplifier, a first resistor, a first capacitor, a second resistor, and a second capacitor. The second capacitor is connected in parallel between the inverting input terminal and an output path of the operational amplifier. The second resistor is connected between the output terminal of the operational amplifier and a second node on a path connecting the input signal to the inverting input terminal. The first resistor is coupled between the first node and inverting input terminal of the operational amplifier. The first capacitor is coupled between the first node and Vss. Due to such connections, the filter circuit operates as a second order filter circuit, thereby providing a desired high level of filtering. Also, as the filter circuit is implemented with a single operational amplifier, the power and area requirements are reduced.

Abstract: A receiver, implemented with low noise and low distortion, to process an input signal containing signals of interest and unwanted interference signal. In an embodiment, the receiver contains a mixer which generates an intermediate signal in the form of an electric current, and a filter which filters the unwanted interference signals from the intermediate signal. The intermediate signal is centered around a lower frequency compared to a crier frequency of the input signal. Due to the current mode interface between the mixer and the filter circuit, low noise and low distortion may be attended.

Abstract: The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).