Abstract: A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set of step coefficients (GP2, GP4) are utilized to determined the step size and thereby the overall gain of the modulator (350). A feedback path is provided and configured to deliver the output of the modulator to a gain control block (355) which provides control and stability across the entire transmission bandwidth. A multilevel digital output (320) is provided which represents levels of signal in the digital domain and reduces the number of discrete components required to achieve a particular amount of gain.

Abstract: A cost-effective filter consuming low power and occupying minimal space. The filter may be used in a ADSL modem (or CPE) to filter the signal components other than the ADSL signals. A high pass filter first filters the low frequency components to attenuate (or remove) lower frequency components such as that caused by ADSL transmit echo signals and that used for voice transmission. The high pass filter may be modified by adding a few resistors to limit the voltages of the high frequency signals also. The output of the high pass filter is amplified and passed through a low pass filter to filter the high frequency components (HPNA included). Due to earlier filtering operation of the high pass filter, the signal can be amplified substantially before being sent to the low pass filter. The implementation of the low pass filter is simplified due to the prior amplification.

Abstract: A filter circuit with two 2nd order stages cascaded in sequence. The first stage is implemented with high quality (Q) factor, and the second stage is implemented with a low Q factor and an imaginary zero. The first stage is designed to further eliminate the unwanted frequency components. The imaginary zero in the second stage eliminates the noise present in the output of the first stage due to the requirement of high Q in the first stage. Any additional noise introduced by the second stage is minimal due to the low Q of the second stage. Each stage may be implemented using only a single operational amplifier when the first stage generates a differential output signal.

Abstract: A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set of step coefficients (GP2, GP4) are utilized to determined the step size and thereby the overall gain of the modulator (350). A feedback path is provided and configured to deliver the output of the modulator to a gain control block (355) which provides control and stability across the entire transmission bandwidth. A multilevel digital output (320) is provided which represents levels of signal in the digital domain and reduces the number of discrete components required to achieve a particular amount of gain.

Abstract: A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set of step coefficients (GP2, GP4) are utilized to determined the step size and thereby the overall gain of the modulator (350). A feedback path is provided and configured to deliver the output of the modulator to a gain control block (355) which provides control and stability across the entire transmission bandwidth. A multilevel digital output (320) is provided which represents levels of signal in the digital domain and reduces the number of discrete components required to achieve a particular amount of gain.

Abstract: A filter circuit with two 2nd order stages cascaded in sequence. The first stage is implemented with high quality (Q) factor, and the second stage is implemented with a low Q factor and an imaginary zero. The first stage is designed to further eliminate the unwanted frequency components. The imaginary zero in the second stage eliminates the noise present in the output of the first stage due to the requirement of high Q in the first stage. Any additional noise introduced by the second stage is minimal due to the low Q of the second stage. Each stage may be implemented using only a single operational amplifier when the first stage generates a differential output signal.

Abstract: A method of providing an improved transfer function for a Discrete Multitone (DMT) type modulation transmitter with digital filtering after modulation followed by digital to analog converter and analog filtering is provided by sending a test signal to said transmitter and measuring the results of the test signal to determine the transfer function. The inverse of the transfer function that needs to be compensated is determined and the inverse of transfer function to be compensated is truncated to the region of interest (H2). The desired band split component of pre-compensation filter is designed (H3). The desired target frequency response of the pre-compensation filter is determined by H4=H2*H3 where H4 is the multiplication of H2 and H3 Given the target frequency response in H4 Hermetian symmetry is imposed on the frequency response. The inverse Fourier transform (IFFT) is taken to generate a time domain filter, h5. The characteristic of this filter is added at the digital filtering after modulation.

Abstract: A T-network containing three impedances is provided between two terminating ends connected to a non-fixed voltage level. Two impedances are connected in series between the two terminating ends. A third impedance is connected between the junction of the first two impedances and a fixed voltage. Switches may be used to trim the third impedance, thus obtaining a desired voltage between the two terminating ends. A terminal of any switches used for trimming can be connected to the fixed voltage node, thereby ensuring that the impedance introduced by the switches does not change substantially during different operating situations.

Abstract: A T-network containing three impedance is provided between two terminating ends not connected to ground. Two impedances may be connected in series between the two terminating ends. A third impedance may be connected between the junction of the first two impedances and a fixed voltage (e.g., ground). Switches may be used to trim the third voltage, thus obtaining a desired voltage between the two terminating ends. A terminal of any switches used for trimming can be connected to the fixed voltage node, thereby ensuring that the impedance introduced by the switches does not change substantially during different operating situations.

Abstract: A method for reducing transmit echo in a DSL modem comprises selecting at least one cancellation device of a plurality of cancellation devices. An attenuation signal is generated using the selected cancellation device. At least a portion of transmit echo is removed from a receive signal using the attenuation signal.

Abstract: The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).

Abstract: The present invention provides a hardware assisted automatic gain control (AGC) for a communication network. A dedicated hardware portion of the AGC, which works in cooperation with software implemented functionality (400), is included to detect saturation conditions in the internal nodes of the analog front end (200) in which a plurality of gain stages (PGA1, PGA2, PGA3) and filter stages (H1, H2, H3) are interleaved with inaccessible intermediate points. The saturation detection logic includes a comparator (21, 22, 23) and flip-flop (27, 28, 29) for each gain stage (PGA1, PGA2, PGA3) and can be integrated directly in the analog front end 200. The dedicated hardware can further be included in a codec of a modem in a digital subscriber line (DSL) system.

Abstract: A modem operating in a narrow voltage range while maintaining a high signal to noise ratio during reception. The modem may contain a coder-decoder (CODEC) and a transformer. The CODEC receives data using more windings of a primary coil than the number of windings used for transmitting. As a result, the turns ratio is higher during transmission, leading to a correspondingly high amplification during transmission. The high amplification in the transmit direction enables the modem to operate in a narrow voltage range. As more windings of the primary coil are used for receiving, a signal of interest received from the telephone line is attenuated to a corresponding lesser degree, which leads to a high signal to noise ratio.