Patents by Inventor Praneet Adusumilli

Praneet Adusumilli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200343448
    Abstract: A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Takashi Ando, Praneet Adusumilli, Jianshi Tang, Reinaldo Vega
  • Publication number: 20200327941
    Abstract: A method is presented for mitigating conductance drift in intercalation cells for neuromorphic computing. The method includes forming a first electro-chemical random access memory (ECRAM) structure over a substrate and forming a second ECRAM over the substrate, the first and second ECRAMs sharing a common contact. The common contact can be either a source contact or a drain contact. Each of the first and second ECRAMs can include a tungsten oxide layer, an electrolyte layer, and a gate contact.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 15, 2020
    Inventors: Jianshi Tang, Praneet Adusumilli, Reinaldo Vega, Takashi Ando
  • Patent number: 10784194
    Abstract: Embedded resistors which have tunable resistive values located between interconnect levels are provided. The embedded resistors have a pillar structure, i.e., they have a height that is greater than their width, thus they occupy less real estate as compared with conventional planar resistors that are typically employed in BEOL technology.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli
  • Publication number: 20200273708
    Abstract: After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10756163
    Abstract: A capacitor structure is provided that includes conformal layers of a lower electrode, a high-k metal oxide dielectric, and an upper electrode. The capacitor structure is formed by a single process which enables the in-situ conformal deposition of the electrode and dielectric layers of the capacitor structure. The single process includes atomic layer deposition in which a metal-containing precursor is selected to provide each of the layers of the capacitor structure. The lower electrode layer is formed by utilizing the metal-containing precursor and a first reactive gas, the high-k metal oxide dielectric layer is provided by switching the first reactive gas to a second reactive gas, and the upper electrode layer is provided by switching the second reactive gas back to the first reactive gas.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10741492
    Abstract: A semiconductor structure is provided in which metal semiconductor alloy pillars are formed at least partially within the sidewall surfaces of each semiconductor fin that extends from a surface of a substrate. These pillars are fuses (i.e., FinFET fuses) that are formed at a very tight pitch dimensions. The pillars can be trimmed after forming FinFET devices. The present application provides a method for forming on-chip FinFET fuses easily by choice of the metal semiconductor alloy, the amount of pillar trim, the number of contacted pillars and to a lower design degree the height of each pillar.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli, Bahman Hekmatshoartabari
  • Patent number: 10734575
    Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Adra Carr, Praneet Adusumilli
  • Patent number: 10727070
    Abstract: A low resistance middle-of-line interconnect structure is formed without liner layers. A contact metal layer is deposited on source/drain regions of field-effect transistors and directly on the surfaces of trenches within a dielectric layer using plasma enhancement. Contact metal fill is subsequently provided by thermal chemical vapor deposition. The use of low-resistivity metal contact materials such as ruthenium is facilitated by the process. The process further facilitates the formation of metal silicide regions on the source/drain regions.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10699949
    Abstract: A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Keith Kwong Hon Wong, Wonwoo Kim, Praneet Adusumilli
  • Patent number: 10692722
    Abstract: After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 23, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10685888
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 10665541
    Abstract: At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or metallic contact region) is provided to each of the openings. The void-free metallization region has the biconvex shape and exhibits a low wire resistance.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Publication number: 20200152860
    Abstract: A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Oscar van der Straten, Alexander Reznicek, Praneet Adusumilli
  • Patent number: 10651042
    Abstract: A method of forming a contact to a semiconductor device that includes forming a vertically orientated channel region on semiconductor material layer of a substrate; and forming a first source/drain region in the semiconductor material layer. The method may continue with forming a metal semiconductor alloy contact on the first source/drain region extending along a horizontally orientated upper surface of the first source/drain region that is substantially perpendicular to the vertically orientated channel region, wherein the metal semiconductor alloy contact extends substantially to an interface with the vertically orientated channel region. Thereafter, a gate structure is formed on the vertically orientated channel region, and a second source/drain region is formed on the vertically orientated channel region.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Publication number: 20200135807
    Abstract: A method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: Kevin W. Brew, Iqbal Rashid Saraf, Injo Ok, Nicole Saulnier, Praneet Adusumilli
  • Publication number: 20200119136
    Abstract: A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Alexander Reznicek, Praneet Adusumilli, Oscar van der Straten, Joshua Rubin
  • Patent number: 10600860
    Abstract: A resistive material is formed straddling over each semiconductor fin that extends upward from a surface of a substrate. The resistive material is then disconnected by removing the resistive material from atop each semiconductor fin. Remaining resistive material in the form of a U-shaped resistive material liner is present between each semiconductor fin. Contact structures are formed perpendicular to each semiconductor fin and contacting a portion of a first set of the semiconductor fins and a first set of the U-shaped resistive material liners.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Shanti Pancharatnam, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10593659
    Abstract: A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon substrate that contains an upper region of undoped silicon and a lower region of n-doped silicon. The lower region of the bulk silicon substrate includes alternating regions of n-doped silicon that have a first boron concentration (i.e., boron deficient regions), and regions of n-doped silicon that have a second boron concentration which is greater than the first boron concentration (i.e., boron rich regions).
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Publication number: 20200083425
    Abstract: A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 12, 2020
    Inventors: Oscar van der Straten, Alexander Reznicek, Praneet Adusumilli
  • Patent number: 10580966
    Abstract: A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Oscar van der Straten, Alexander Reznicek, Praneet Adusumilli