Abstract: A method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element.

Abstract: A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.

Abstract: A resistive material is formed straddling over each semiconductor fin that extends upward from a surface of a substrate. The resistive material is then disconnected by removing the resistive material from atop each semiconductor fin. Remaining resistive material in the form of a U-shaped resistive material liner is present between each semiconductor fin. Contact structures are formed perpendicular to each semiconductor fin and contacting a portion of a first set of the semiconductor fins and a first set of the U-shaped resistive material liners.

Abstract: A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon substrate that contains an upper region of undoped silicon and a lower region of n-doped silicon. The lower region of the bulk silicon substrate includes alternating regions of n-doped silicon that have a first boron concentration (i.e., boron deficient regions), and regions of n-doped silicon that have a second boron concentration which is greater than the first boron concentration (i.e., boron rich regions).

Abstract: A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.

Abstract: A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.

Abstract: A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.

Abstract: A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.

Abstract: A semiconductor structure is provided in which metal semiconductor alloy pillars are formed at least partially within the sidewall surfaces of each semiconductor fin that extends from a surface of a substrate. These pillars are fuses (i.e., FinFET fuses) that are formed at a very tight pitch dimensions. The pillars can be trimmed after forming FinFET devices. The present application provides a method for forming on-chip FinFET fuses easily by choice of the metal semiconductor alloy, the amount of pillar trim, the number of contacted pillars and to a lower design degree the height of each pillar.

Abstract: A method for forming a salicide includes forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape, forming a conductive material on the (111) facet, annealing the conductive material to form a silicide on the (111) facet, and forming at least one contact to the silicide.

Abstract: A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.

Abstract: Metal-on-metal insulator structures and methods for making the same. The method includes: providing an insulator layer overlying a semiconductor substrate, forming a plurality of alternating first conductive layers and second conductive layers on the insulator layer, forming at least one dielectric layer between each of the alternating first conductive layers and second conductive layers, forming a first trench at a first location through a first portion of the plurality of the alternating first conductive layers and second conductive layers and the at least one dielectric layer, and first etching the first trench selective to the plurality of alternating first conductive layers and second conductive layers, wherein the first conductive layers are etched faster than the second conductive layers to form a first modified trench, wherein the first conductive layers are recessed relative to the center of the first modified trench greater than the second conductive layers.

Abstract: A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.

Abstract: A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.

Abstract: A semiconductor structure is provided in which metal semiconductor alloy pillars are formed at least partially within the sidewall surfaces of each semiconductor fin that extends from a surface of a substrate. These pillars are fuses (i.e., FinFET fuses) that are formed at a very tight pitch dimensions. The pillars can be trimmed after forming FinFET devices. The present application provides a method for forming on-chip FinFET fuses easily by choice of the metal semiconductor alloy, the amount of pillar trim, the number of contacted pillars and to a lower design degree the height of each pillar.

Abstract: An antifuse is provided that is embedded in a semiconductor substrate. The antifuse has a large contact area, and a reduced breakdown voltage. After blowing the antifuse, the antifuse has a low resistance. The antifuse may have a single breakdown point or multiple breakdown points. The antifuse includes a metal or metal alloy structure that is separated from a doped semiconductor material portion of the semiconductor substrate by an antifuse dielectric material liner. The metal or metal alloy structure and the antifuse dielectric material liner have topmost surfaces that are coplanar with each other as well as being coplanar with a topmost surface of the semiconductor substrate.

Abstract: At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or metallic contact region) is provided to each of the openings. The void-free metallization region has the biconvex shape and exhibits a low wire resistance.

Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.

Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.

Abstract: At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or metallic contact region) is provided to each of the openings. The void-free metallization region has the biconvex shape and exhibits a low wire resistance.