Abstract: A method for forming a semiconductor structure is disclosed. The method provides a substrate with an insulator pad overlying at least a top portion of the substrate. The method further includes forming a plurality of dielectric columns overlying the substrate and the dielectric pad. Each dielectric column is separated from another dielectric column to form a corresponding plurality of aspect-ration trapping (ART) trenches. The insulator pad spans a bottom portion of a first ART trench of the plurality of ART trenches. A portion of the substrate spans a bottom portion of a second ART trench of the plurality of ART trenches. The method further includes forming a III-V semiconductor material stack in the second ART trench. The method further includes forming a first resistive region in the first ART trench, wherein the first resistive region is in contact with the insulator pad.

Abstract: Metal-on-metal insulator structures and methods for making the same. The method includes: providing an insulator layer overlying a semiconductor substrate, forming a plurality of alternating first conductive layers and second conductive layers on the insulator layer, forming at least one dielectric layer between each of the alternating first conductive layers and second conductive layers, forming a first trench at a first location through a first portion of the plurality of the alternating first conductive layers and second conductive layers and the at least one dielectric layer, and first etching the first trench selective to the plurality of alternating first conductive layers and second conductive layers, wherein the first conductive layers are etched faster than the second conductive layers to form a first modified trench, wherein the first conductive layers are recessed relative to the center of the first modified trench greater than the second conductive layers.

Abstract: Embedded resistors which have tunable resistive values located between interconnect levels are provided. The embedded resistors have a pillar structure, i.e., they have a height that is greater than their width, thus they occupy less real estate as compared with conventional planar resistors that are typically employed in BEOL technology.

Abstract: A method for forming a semiconductor structure is disclosed. The method provides a substrate with an insulator pad overlying at least a top portion of the substrate. The method further includes forming a plurality of dielectric columns overlying the substrate and the dielectric pad. Each dielectric column is separated from another dielectric column to form a corresponding plurality of aspect-ration trapping (ART) trenches. The insulator pad spans a bottom portion of a first ART trench of the plurality of ART trenches. A portion of the substrate spans a bottom portion of a second ART trench of the plurality of ART trenches. The method further includes forming a III-V semiconductor material stack in the second ART trench. The method further includes forming a first resistive region in the first ART trench, wherein the first resistive region is in contact with the insulator pad.

Abstract: A semiconductor device includes epitaxially grown source/drain (S/D) regions each having a cross-sectional quadrilateral shape formed on a semiconductor fin on opposite sides of a transversely disposed gate structure. The S/D regions include top (111) facets on top halves of the cross-sectional quadrilateral shape. The device further includes a silicide formed on the top (111) facets.

Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.

Abstract: A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.

Abstract: Metal-on-metal insulator structures and methods for making the same. The method includes: providing an insulator layer overlying a semiconductor substrate, forming a plurality of alternating first conductive layers and second conductive layers on the insulator layer, forming at least one dielectric layer between each of the alternating first conductive layers and second conductive layers, forming a first trench at a first location through a first portion of the plurality of the alternating first conductive layers and second conductive layers and the at least one dielectric layer, and first etching the first trench selective to the plurality of alternating first conductive layers and second conductive layers, wherein the first conductive layers are etched faster than the second conductive layers to form a first modified trench, wherein the first conductive layers are recessed relative to the center of the first modified trench greater than the second conductive layers.

Abstract: A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.

Abstract: A capacitor structure is provided that includes conformal layers of a lower electrode, a high-k metal oxide dielectric, and an upper electrode. The capacitor structure is formed by a single process which enables the in-situ conformal deposition of the electrode and dielectric layers of the capacitor structure. The single process includes atomic layer deposition in which a metal-containing precursor is selected to provide each of the layers of the capacitor structure. The lower electrode layer is formed by utilizing the metal-containing precursor and a first reactive gas, the high-k metal oxide dielectric layer is provided by switching the first reactive gas to a second reactive gas, and the upper electrode layer is provided by switching the second reactive gas back to the first reactive gas.

Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.

Abstract: An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier liner that is located in an opening present in an interconnect dielectric material layer. An interconnect metal or metal alloy structure is present on physically exposed sidewalls of the seed enhancement spacer and on the physically exposed horizontal surface of the diffusion barrier liner.

Abstract: A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.

Abstract: Method and apparatus for a capacitive structure. The capacitive structure includes a material stack having a deep trench formed therein. The material stack includes alternating vertical and semi-ovoid sidewall surfaces. The material stack further includes alternating metallization layers and dielectric layers. At least one of the semi-spheroidal sidewall surfaces is formed in a sidewall of at least one of the dielectric layers in the deep trench. At least one of the vertical sidewall surfaces is a sidewall surface of at least one metallization layer in the deep trench.

Abstract: Embedded resistors which have tunable resistive values located between interconnect levels are provided. The embedded resistors have a pillar structure, i.e., they have a height that is greater than their width, thus they occupy less real estate as compared with conventional planar resistors that are typically employed in BEOL technology.

Abstract: A strain relaxed silicon germanium layer that has a low defect density is formed on a surface of a silicon substrate without causing wafer bowing. The strain relaxed silicon germanium layer is formed using multiple epitaxial growing, bonding and transferring steps. In the present application, a thick silicon germanium layer having a low defect density is grown on a transferred portion of a topmost silicon germanium sub-layer of an initial strain relaxed silicon germanium graded buffer layer and then bonded to a silicon substrate. A portion of the thick silicon germanium layer is then transferred to the silicon substrate. Additional steps of growing a thick silicon germanium layer having a low defect density, bonding and layer transfer may be performed as necessary.

Abstract: A structure is provided that includes a lower interconnect level that includes a first interconnect dielectric material layer having an opening that contains a first bimetallization interconnect structure. An upper interconnect level is located above the lower interconnect level. The upper interconnect level includes a second interconnect dielectric material layer having a combined via/line opening, wherein the line portion of the combined via/line opening contains a second bimetallization interconnect structure.

Abstract: A capacitor structure is provided that includes conformal layers of a lower electrode, a high-k metal oxide dielectric, and an upper electrode. The capacitor structure is formed by a single process which enables the in-situ conformal deposition of the electrode and dielectric layers of the capacitor structure. The single process includes atomic layer deposition in which a metal-containing precursor is selected to provide each of the layers of the capacitor structure. The lower electrode layer is formed by utilizing the metal-containing precursor and a first reactive gas, the high-k metal oxide dielectric layer is provided by switching the first reactive gas to a second reactive gas, and the upper electrode layer is provided by switching the second reactive gas back to the first reactive gas.

Abstract: A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.

Abstract: Low resistivity, wrap-around contact structures are provided in nanosheet devices, vertical FETs, and FinFETs. Such contact structures are obtained by delivering dopants to source/drain regions using a highly conformal, doped metal layer. The conformal, doped metal layer may be formed by ALD or CVD using a titanium tetraiodide precursor. Dopants within the conformal, doped metal layer are delivered during the formation of wrap-around metal silicide or metal germano-silicide regions. Dopant segregation at silicide/silicon interfaces or germano-silicide/silicon interfaces reduces contact resistance in the wrap-around contact structures. A contact metal layer electrically communicates with the wrap-around contact structures.