Abstract: Disclosed herein are memory devices with a logic region between memory regions. For example, in some embodiments, a memory device may include: a first memory region; a second memory region; a logic region between the first memory region and the second memory region; and a metallization stack, wherein the first memory region is between the logic region and the metallization stack.

Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.

Abstract: Spin transfer torque memory (STTM) devices incorporating an Insulator-Metal-Transition (IMT) device or at least one layer of Insulator-Metal-Transition (IMT) material are disclosed. The Insulator-Metal-Transition (IMT) device or at least one layer of Insulator-Metal-Transition (IMT) material are utilized for providing a spike current when the voltage across it exceeds the threshold voltage to reduce a critical current required for transfer torque induced magnetization switching.

Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

Abstract: Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.

Abstract: Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memtory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.

Abstract: Embodiments of the present disclosure are directed towards techniques to provide a memory device with reduced capacitance. In one embodiment, a memory array is formed in a die, and includes one or more pillars and a plurality of wordlines coupled with the one or more pillars. Adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, which may include components, to reduce capacitance of the plurality of wordlines. The components comprise air gaps or low-k dielectric material. Other embodiments may be described and/or claimed.

Abstract: A memory structure can include a conductive channel, a charge storage structure adjacent to the conductive channel, and a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure. The strain-inducing layer can have a higher coefficient of thermal expansion (CTE) than the conductive channel.

Abstract: Diffractive optical elements for wide field-of-view virtual reality devices and methods of manufacturing the same are disclosed. An example apparatus includes a substrate and a thin film stack including alternating layers of a first material and a second material. The thin film stack defines an annular protrusion. The annular protrusion has a stair-like profile. Top surfaces of separate ones of steps in the stair-like profile correspond to top surfaces of separate ones of the layers of the second material.

Abstract: An embodiment includes an apparatus comprising: a memory array comprising: a selector switch including top and bottom electrodes, a metal layer, and a solid electrolyte layer; a memory cell in series with the selector switch; bit and write lines, wherein (a) (i) the top electrode couples to one of the bit and write lines and the bottom electrode couples to another of the bit and write lines, and (a) (ii) the memory cell is between one of the top and bottom electrodes and one of the bit and write lines; wherein (b) (i) the metal layer includes silver (Ag), and (b) (ii) Ag ions from the metal layer form a conductive path in the SE layer when the top electrode is biased and disband the conductive path when the top electrode is not biased. Other embodiments Electrode are described herein.

Abstract: Spin transfer torque memory (STTM) devices incorporating an Insulator-Metal-Transition (IMT) device or at least one layer of Insulator-Metal-Transition (IMT) material are disclosed. The Insulator-Metal-Transition (IMT) device or at least one layer of Insulator-Metal-Transition (IMT) material are utilized for providing a spike current when the voltage across it exceeds the threshold voltage to reduce a critical current required for transfer torque induced magnetization switching.

Abstract: An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memory blocks including orthogonally arranged conductive lines, and memory elements at cross-sections of the conductive lines. A first plurality of sockets is on the first die adjacent to the memory blocks, the first plurality of sockets comprising a first plurality of pads that connect to at least a portion to the conductive lines of the corresponding memory block. A second die includes logic circuitry and a second plurality of sockets comprising a second plurality of pads at least partially aligned with positions of the first plurality of pads on the first die. A top of the first die and a top of the second die face one another, wherein the first plurality of pads are bonded with the second plurality pads to directly connect the cross-point memory array to the logic circuitry.

Abstract: An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the middle layer includes material that has a first resistance when the first electrode is biased at a first voltage level and a second resistance when the first electrode is biased at a second voltage level; (b) the first resistance is less than the second resistance and the first voltage level is greater than the second voltage level. Other embodiments are described herein.

Abstract: Electronic devices, memory devices, and computing devices are disclosed. An electronic device includes electronic circuitry, a temperature sensor, a heat sink, at least one thermoelectric material, a thermally conductive material configured to thermally couple the electronic circuitry to the at least one thermoelectric material, and a transistor. The temperature sensor is configured to monitor a temperature of the electronic circuitry. The transistor is configured to selectively enable thermoelectric current to flow through the at least one thermoelectric material and dissipate heat from the thermally conductive material to the heat sink responsive to fluctuations in the temperature of the electronic circuitry detected by the temperature sensor.

Abstract: Embodiments of the present disclosure are directed towards a memory device with vertical string drivers, in accordance with some embodiments. In one embodiment, the memory device includes a plurality of wordlines formed in a stack of multiple tiers. The device further includes a semiconductor layer disposed on top of the plurality of wordlines. The device further includes a plurality of string drivers disposed in the semiconductor layer substantially perpendicular to the tier stack of the plurality of wordlines. The semiconductor layer provides respective gate connections for the plurality of string drivers. In some embodiments, the semiconductor layer may be fabricated of polysilicon. Other embodiments may be described and/or claimed.

Abstract: Embedded non-volatile memory structures having an independently sized selector element and memory element are described. In an example, a memory device includes a metal layer. A selector element is above the metal layer. A memory element is above the metal line. A spacer surrounds one of the selector element and the memory element having a smallest width, and wherein the one of the selector element and the memory element not surrounded by the spacer has a width substantially identical to the spacer and is in alignment with the spacer.

Abstract: IC device including back-end-of-line (BEOL) transistors with crystalline channel material. A BEOL crystalline seed may be formed over a dielectric layer that has been planarized over a front-end-of-line (FEOL) transistor level that employs a monocrystalline substrate semiconductor. The BEOL crystalline seed may be epitaxial to the substrate semiconductor, or may have crystallinity independent of that of the substrate semiconductor. The BEOL crystalline seed may comprise a first material having a higher melt temperature than a melt material formed over the seed and over the dielectric layer. Through rapid melt growth, the melt material may be heated to a temperature sufficient to transition from an as-deposited state to a more crystalline state that is derived from, and therefore associated with, the BEOL crystalline seed. A BEOL transistor may then be fabricated from the crystallized material.

Abstract: Embodiments herein describe techniques for a semiconductor device including a SRAM device having multiple SRAM memory cells, and a capacitor coupled to the SRAM device. The capacitor includes a first plate, a second plate, and a capacitor dielectric layer between the first plate and the second plate. The capacitor is to supply power to the multiple SRAM memory cells of the SRAM device in parallel for a period of time. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for an optical device including a substrate of a wafer. An image sensor device is formed on a front side of the substrate, while a plurality of posts of a metasurface lens are formed on a backside opposite to the front side of the substrate. A post of the plurality of posts includes a metasurface material that is transparent to light. Other embodiments may be described and/or claimed.

Abstract: A thin film transistor (TFT) to control a light emitting diode (LED) or an organic light emitting diode (OLED) includes a channel region configured as a saddle channel extending between the drain region and the source region of the TFT. The saddle channel is formed by deposition of channel material on a fin structure, and the contour of the saddle channel is defined by the contour of the fin structure. Deposition of the channel material for the saddle channel may be performed by: (i) atomic layer deposition (ALD) of amorphous silicon; (ii) ALD of amorphous silicon followed by annealing to form polycrystalline silicon; or (iii) deposition of indium gallium zinc oxide (IGZO) material by one of ALD, plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).