Patents by Inventor Prashant Majhi

Prashant Majhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DEUTERIUM-BASED PASSIVATION OF NON-PLANAR TRANSISTOR INTERFACES
    Publication number: 20200286996
    Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 10, 2020
    Applicant: INTEL CORPORATION
    Inventors: PRASHANT MAJHI, GLENN A. GLASS, ANAND S. MURTHY, TAHIR GHANI, ARAVIND S. KILLAMPALLI, MARK R. BRAZIER, JAYA P. GUPTA
  • ANTIFERROELECTRIC GATE DIELECTRIC TRANSISTORS AND THEIR METHODS OF FABRICATION
    Publication number: 20200273962
    Abstract: A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.
    Type: Application
    Filed: January 12, 2018
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Brian S. Doyle, Abhishek A. Sharma, Prashant Majhi, Willy Rachmady, Jack T. Kavalieros, Gilbert Dewey
  • DYNAMIC RANDOM ACCESS MEMORY INCLUDING THRESHOLD SWITCH
    Publication number: 20200251160
    Abstract: Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.
    Type: Application
    Filed: September 28, 2017
    Publication date: August 6, 2020
    Inventors: ABHISHEK A. SHARMA, RAVI PILLARISETTY, BRIAN S. DOYLE, PRASHANT MAJHI
  • Heterojunction TFETs employing an oxide semiconductor
    Patent number: 10734513
    Abstract: Heterojunction tunnel field effect transistors (hTFETs) incorporating one or more oxide semiconductor and a band offset between at least one of a channel material, a source material of a first conductivity type, and drain of a second conductivity type, complementary to the first. In some embodiments, at least one of p-type material, channel material and n-type material comprises an oxide semiconductor. In some embodiments, two or more of p-type material, channel material, and n-type material comprises an oxide semiconductor. In some n-type hTFET embodiments, all of p-type, channel, and n-type materials are oxide semiconductors with a type-II or type-III band offset between the p-type and channel material.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Jack T. Kavalieros, Elijah V. Karpov, Uday Shah, Ravi Pillarisetty
  • 2S-1C 4F2 CROSS-POINT DRAM ARRAY
    Publication number: 20200243543
    Abstract: A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 30, 2020
    Inventors: Ravi PILLARISETTY, Abhishek A. SHARMA, Prashant MAJHI, Elijah V. KARPOV, Brian S. DOYLE
  • 3D NAND structures including group III-N material channels
    Patent number: 10727241
    Abstract: Techniques are disclosed for forming three-dimensional (3D) NAND structures including group III-nitride (III-N) material channels. Typically, polycrystalline silicon (poly-Si) channels are used for 3D NAND structures, such as 3D NAND flash memory devices. However, using III-N channel material for 3D NAND structures offers numerous benefits over poly-Si channel material, such as relatively lower resistance in the channel, relatively higher current densities, and relatively lower leakage. Therefore, using III-N channel material enables an increased number of floating gates or storage cells to be stacked in 3D NAND structures, thereby leading to increased capacity for a given integrated circuit footprint (e.g., increased GB/cm2). For instance, use of III-N channel material can enable greater than 100 floating gates for a 3D NAND structure. Other embodiments may be described and/or disclosed.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Prashant Majhi, Han Wui Then, Marko Radosavljevic
  • LOW RESISTANCE FIELD-EFFECT TRANSISTORS AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20200235244
    Abstract: Low resistance field-effect transistors and methods of manufacturing the same are disclosed herein. An example field-effect transistor disclosed herein includes a substrate and a stack above the substrate. The stack includes an insulator and a gate electrode. The example field-effect transistor includes a semiconductor material layer in a cavity in the stack. In the example field-effect transistor, a region of the semiconductor material layer proximate to the insulator is doped with a material of the insulator.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Brian Doyle, Abhishek Sharma, Elijah Karpov, Ravi Pillarisetty, Prashant Majhi
  • DOUBLE SELECTOR ELEMENT FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES
    Publication number: 20200235162
    Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.
    Type: Application
    Filed: September 27, 2017
    Publication date: July 23, 2020
    Inventors: Prashant MAJHI, Ravi PILLARISETTY, Elijah V. KARPOV, Brian S. DOYLE, Abhishek A. SHARMA
  • FERROELECTRIC GATE DIELECTRICS IN INTEGRATED CIRCUITS
    Publication number: 20200235221
    Abstract: In various embodiments disclosed herein are systems, methods, and apparatuses for using a ferroelectric material as a gate dielectric in an integrated circuit, for example, as part of a transistor. In an embodiment, the transistor can include a p-type metal oxide semiconductor (PMOS) transistor. In an embodiment, the transistor can have a p-doped substrate. In an embodiment, the channel of the transistor can be a p-doped channel. In an embodiment, the transistor having the ferroelectric material as the gate dielectric can be used in connection with an inverter. In an embodiment, the inverter can be used in connection with an static random access memory (SRAM) memory device.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Prashant Majhi, Ravi Pillarisetty, Elijah V. Karpov
  • 1S-1T FERROELECTRIC MEMORY
    Publication number: 20200234750
    Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 23, 2020
    Applicant: INTEL CORPORATION
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov
  • SRAM USING 2T-2S
    Publication number: 20200235105
    Abstract: A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some embodiments. The term 1T-1S refers to a transistor in series with a selector device. Accordingly, the term 2T-2S refers to two such 1T-1S structures.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 23, 2020
    Applicant: INTEL CORPORATION
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi
  • SELECTOR DEVICES
    Publication number: 20200235163
    Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include germanium, tellurium, and sulfur.
    Type: Application
    Filed: September 14, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Elijah V. Karpov, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Abhishek A. Sharma
  • SELECTOR ELEMENT WITH BALLAST FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES
    Publication number: 20200227477
    Abstract: Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.
    Type: Application
    Filed: September 13, 2017
    Publication date: July 16, 2020
    Inventors: Prashant MAJHI, Ravi PILLARISETTY, Elijah V. KARPOV, Brian S. DOYLE, Abhishek A. SHARMA
  • Apparatus with multi-wafer based device comprising embedded active and/or passive devices and method for forming such
    Patent number: 10714446
    Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Anup Pancholi, Prashant Majhi, Paul Fischer, Patrick Morrow
  • VERTICAL SWITCHING DEVICE WITH SELF-ALIGNED CONTACT
    Publication number: 20200220023
    Abstract: An embodiment includes a system comprising: a thin film transistor (TFT) comprising a source, a channel, a drain, and a gate; first, second, and third dielectric portions; wherein (a) a first vertical axis intersects the source, the channel, and the drain; (b) the first dielectric portion surrounds the source in a first plane; (c) the second dielectric portion surrounds the channel in a second plane; (d) the third dielectric surrounds the drain in a third plane; (e) a second vertical axis intersects the first, second, and third dielectric portions; (f) the source includes a first dopant, the first dielectric portion includes the first dopant, the second dielectric portion includes at least one of the first dopant and a second dopant, the drain includes the at least one of the first and second dopants, and the third dielectric portion includes the at least one of the first and second dopants.
    Type: Application
    Filed: January 4, 2018
    Publication date: July 9, 2020
    Inventors: Ravi Pillarisetty, Prashant Majhi, Seung Hoon Sung, Willy Rachmady, Gilbert Dewey, Abhishek A. Sharma, Brian S. Doyle, Jack T. Kavalieros
  • Integrated 1T1R RRAM memory cell
    Patent number: 10706921
    Abstract: One embodiment provides an apparatus. The apparatus includes a bipolar junction transistor (BJT) and an integrated resistive element. The BJT includes a base contact, a base region, a collector contact, a collector region and an integrated emitter contact. The integrated resistive element includes a resistive layer and an integrated electrode. The resistive element is positioned between the base region and the integrated emitter contact.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 7, 2020
    Assignee: INTEL CORPORATION
    Inventors: Elijah V. Karpov, Ravi Pillarisetty, Prashant Majhi, Niloy Mukherjee, Uday Shah
  • ASYMMETRIC SELECTOR ELEMENT FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES
    Publication number: 20200212105
    Abstract: Embedded non-volatile memory structures having asymmetric selector elements are described. In an example, a memory device includes a word line. An asymmetric selector element is above the word line. The asymmetric selector element includes a first electrode material layer, a selector material layer on the first electrode material layer, and a second electrode material layer on the selector material layer, the second electrode material layer different in composition than the first electrode material layer. A bipolar memory element is above the word line, the bipolar memory element on the asymmetric selector element. A bit line is above the word line.
    Type: Application
    Filed: September 27, 2017
    Publication date: July 2, 2020
    Inventors: Prashant MAJHI, Abhishek A. SHARMA, Elijah V. KARPOV, Ravi PILLARISETTY, Brian S. DOYLE
  • THIN FILM TRANSISTORS HAVING RELATIVELY INCREASED WIDTH AND SHARED BITLINES
    Publication number: 20200212075
    Abstract: Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.
    Type: Application
    Filed: September 26, 2017
    Publication date: July 2, 2020
    Inventors: Brian S. DOYLE, Abhishek A. SHARMA, Ravi PILLARISETTY, Prashant MAJHI, Elijah V. KARPOV
  • METAL FILAMENT MEMORY CELLS
    Publication number: 20200203604
    Abstract: Disclosed herein are metal filament memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a transistor having a source/drain region; and a metal filament memory device including an active metal and an electrolyte; wherein the electrolyte is coupled between the active metal and the source/drain region when the transistor is an n-type metal oxide semiconductor (NMOS) transistor, and the active metal is coupled between the electrolyte and the source/drain region when the transistor is a p-type metal oxide semiconductor (PMOS) transistor.
    Type: Application
    Filed: September 25, 2016
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Elijah V. Karpov, Prashant Majhi, Niloy Mukherjee
  • THIN-FILM-TRANSISTOR BASED COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) CIRCUIT
    Publication number: 20200203432
    Abstract: Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Willy RACHMADY, Prashant MAJHI, Ravi PILLARISETTY, Elijah KARPOV, Brian DOYLE, Anup PANCHOLI, Abhishek SHARMA