Abstract: Embodiments disclosed herein comprise a ferroelectric material layer and methods of forming such materials. In an embodiment, the ferroelectric material layer comprises hafnium oxide with an orthorhombic phase. In an embodiment, the ferroelectric material layer may also comprise trace elements of a working gas. Additional embodiments may comprise: a semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, a gate electrode over the semiconductor channel, and a gate dielectric between the gate electrode and the semiconductor channel. In an embodiment, the gate dielectric includes a ferroelectric hafnium oxide. In an embodiment, the hafnium oxide is substantially free from dopants.

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.

Abstract: Integrated circuits including 3D memory structures are disclosed. Air-gaps are purposefully introduced between word lines. The word lines may be horizontal or vertical.

Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; a first oxide layer between the OEL and the bottom electrode; and a second oxide layer between the first oxide layer and the bottom electrode; wherein (a) a first plurality of oxygen vacancies are within the first oxide layer and are adjacent the OEL at a first concentration, (b) a second plurality of oxygen vacancies are within the first oxide layer and are adjacent the second oxide layer at a second concentration that is less than the first concentration, and (c) the first oxide layer includes a first oxide material different from a second oxide material included in the second oxide layer. Other embodiments are described herein.

Abstract: Described is a memory cell which comprises: a transistor positioned in a backend of a die, the transistor comprising: a source structure and a drain structure; a gate structure between the source structure and the drain structure; a source contact coupled to and above the source structure and a drain contact coupled to and below the drain structure; and a Resistive Random Access Memory (RRAM) device coupled to the drain contact.

Abstract: An embodiment includes a resistive random access memory (RRAM) comprising: top and bottom electrodes; first and second oxygen exchange layers (OELs) between the top and bottom electrodes; an oxide layer between the first and second OELs; wherein (a) first oxygen vacancies are within an upper third of the oxide layer at a first concentration, (b) second oxygen vacancies are within a lower third of the oxide layer at a second concentration, and (c) third oxygen vacancies are within a middle third of the oxide layer at a third concentration that is less than either of the first and second concentrations. Other embodiments are described herein.

Abstract: Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a source junction, a gate, a drain junction, a semiconductor located below the gate and between the source junction and the drain junction, and an insulator located below the semiconductor. The semiconductor can be used to tune a terminal voltage (Vt). In an example, the semiconductor is an extremely thin silicon on an insulator. In another example, the semiconductor is a fully depleted silicon-on-insulator or an extremely thin silicon on an insulator.

Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

Abstract: A 1T-1R memory cell includes a transistor structure where an ambipolar layer is disposed on an insulator layer formed on a substrate. The transistor further includes a gate dielectric layer that is disposed on the ambipolar layer and a gate electrode disposed on the gate dielectric layer. A source region and a drain region are disposed on the ambipolar layer. The source region is separated from the drain region by the gate electrode. A source contact is disposed on the source region and a drain contact disposed on the drain region. The 1T-1R cell further includes a memory device that is disposed above the drain contact of the transistor. The memory device belongs to a class of memory devices that is based on resistive switching.

Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Abstract: An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Abstract: Electronic devices, memory devices, and computing devices are disclosed. An electronic device includes electronic circuitry, a temperature sensor, a heat sink, at least one thermoelectric material, a thermally conductive material configured to thermally couple the electronic circuitry to the at least one thermoelectric material, and a transistor. The temperature sensor is configured to monitor a temperature of the electronic circuitry. The transistor is configured to selectively enable thermoelectric current to flow through the at least one thermoelectric material and dissipate heat from the thermally conductive material to the heat sink responsive to fluctuations in the temperature of the electronic circuitry detected by the temperature sensor.

Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; a second active device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first set and the second active device, wherein the layer is to bond the one of the layers of the first set and the second active device.

Abstract: Electronic devices, integrated circuit device structures, and computing devices including thin film, diode-based temperature sensors are disclosed. An electronic device includes a diode including diode materials between a first contact and a second contact, a device layer of an integrated circuit device structure, and at least a portion of an interlayer dielectric between the diode and the device layer.

Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

Abstract: A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises of the first material, wherein the second structure is between the first and third structures. Other embodiments are also disclosed and claimed.

Abstract: An integrated circuit structure includes: a field-effect transistor including a semiconductor region including a semiconductor material having a bandgap less than or equal to that of silicon, a semiconductor source and a semiconductor drain, the semiconductor region being between the semiconductor source and the semiconductor drain, a gate electrode, a gate dielectric between the semiconductor region and the gate electrode, a source contact adjacent to the semiconductor source, and a drain contact adjacent to the semiconductor drain; and a resistive switch or a capacitor electrically connected to the drain contact. One of the source contact and the drain contact includes a threshold switching region, to be a selector for the resistive switch or the capacitor. In some embodiments, the threshold switching region includes a threshold switching oxide or a threshold switching chalcogenide, and the resistive switch or the capacitor is part of a resistive memory cell or capacitive memory cell.

Abstract: Selector-based electronic devices, inverters, memory devices, and computing devices include a first selector and a second selector. The first selector and the second selector are electrically connected in series between a first voltage source terminal and a second voltage source terminal. The electronic device also includes a transistor electrically connected between an input terminal and a terminal between the first selector and the second selector.

Abstract: A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium dioxide (TiOx), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.