Patents by Inventor Pratik A. PATEL
Pratik A. PATEL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11664452Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: GrantFiled: October 30, 2020Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Pratik A. Patel, Mark Y. Liu, Jami A. Wiedemer, Paul A. Packan
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Patent number: 11645629Abstract: Technologies for providing real-time visualizations of a behavior of an autonomous vehicle (AV) associated with a ride request. In some examples, a method for providing real-time visualizations of a behavior of an AV associated with a ride request can include receiving a user request for a ride from an AV, wherein the user request specifies a pick-up location associated with a user; receiving sensor data from one or more sensors associated with the AV; determining, based on the sensor data, a state and context of the AV while the AV is en route to the pick-up location; and presenting, at a display interface, a map depicting one or more visual indicators of the state and context of the AV, the state and context of the AV including a location of the AV and one or more AV operations.Type: GrantFiled: September 12, 2019Date of Patent: May 9, 2023Assignee: GM Cruise Holdings LLC.Inventors: Jessica Leary, Jonathon Staff, John Logan Anderson, Max Meyers, Pratik Patel, Robin Yang, Bradley Ryan, Josh Berlin, Teresa Lin, Stanley Shiao, Michael Magnoli, Chau-Yan Wang, Christopher Fry
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Publication number: 20230131126Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.Type: ApplicationFiled: December 23, 2022Publication date: April 27, 2023Inventors: Szuya S. LIAO, Rahul PANDEY, Rishabh MEHANDRU, Anupama BOWONDER, Pratik PATEL
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Publication number: 20230095191Abstract: Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Koustav Ganguly, Ryan Keech, Anand Murthy, Mohammad Hasan, Pratik Patel, Tahir Ghani, Subrina Rafique
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Patent number: 11610691Abstract: A system configured to receive health data pertaining to a user; select a user health profile from a plurality of user health profiles based on the collected health data, each of the plurality of user health profiles being associated with a health and wellness program and a set of interventions; receive user activity data and updated health data pertaining to, or during the user's participation in the associated health and wellness program from health devices; select a new set of interventions based on the user activity data; and select a new user health profile from the plurality of user health profiles based on at least one of the user activity data and the updated health data.Type: GrantFiled: April 1, 2016Date of Patent: March 21, 2023Assignee: MD REVOLUTION, INC.Inventors: Samir B. Damani, Vincent Valentino, Pratik Patel
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Publication number: 20230084182Abstract: Techniques are provided herein to form semiconductor devices having a different number of semiconductor nanoribbons compared to other semiconductor devices on the same substrate. In one example, two different semiconductor devices of a given memory cell, such as a random access memory (RAM) cell, include a p-channel device and an n-channel device. More specifically, the p-channel device may be a GAA transistor with a first number of semiconductor nanoribbons while the n-channel device may be a GAA transistor with a second number of semiconductor nanoribbons that is greater than the first number of semiconductor nanoribbons. In some cases, the n-channel device(s) have one additional semiconductor nanoribbon compared to the p-channel device(s). Depending on when the nanoribbons are removed during the fabrication process, different structural outcomes will occur that can be detected in the final device.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Applicant: Intel CorporationInventors: Mohammad Hasan, Tahir Ghani, Pratik A. Patel, Mohit K. Haran, Leonard P. Guler, Clifford L. Ong
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Publication number: 20230079586Abstract: Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Applicant: Intel CorporationInventors: Mohammad Hasan, Tahir Ghani, Pratik A. Patel, Leonard P. Guler, Mohit K. Haran, Clifford L. Ong
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Publication number: 20220165855Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.Type: ApplicationFiled: February 8, 2022Publication date: May 26, 2022Inventors: Rishabh MEHANDRU, Pratik A. PATEL, Thomas T. TROEGER, Szuya S. LIAO
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Patent number: 11282930Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.Type: GrantFiled: October 30, 2020Date of Patent: March 22, 2022Assignee: Intel CorporationInventors: Rishabh Mehandru, Pratik A. Patel, Thomas T. Troeger, Szuya S. Liao
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Publication number: 20220077311Abstract: A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 19, 2021Publication date: March 10, 2022Applicant: Intel CorporationInventors: Szuya S. Liao, Pratik A. Patel
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Publication number: 20220006459Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Miguel Bautista Gabriel, Sriram Vangal, Patrick Koeberl, Pratik Patel, Muhammad Khellah, James Tschanz, Carlos Tokunaga, Suyoung Bang
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Publication number: 20210408275Abstract: Integrated circuit structures having high surface germanium concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure has an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure has an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 55% at a top surface of each of the epitaxial structures of the first and second source or drain structures.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Cory BOMBERGER, Suresh VISHWANATH, Pratik PATEL, Szuya S. LIAO, Anand S. MURTHY
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Publication number: 20210407851Abstract: Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Cory BOMBERGER, Suresh VISHWANATH, Yulia TOLSTOVA, Pratik PATEL, Szuya S. LIAO, Anand S. MURTHY
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Patent number: 11183592Abstract: A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.Type: GrantFiled: July 1, 2016Date of Patent: November 23, 2021Assignee: Intel CorporationInventors: Szuya S. Liao, Pratik A. Patel
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Patent number: 11152461Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.Type: GrantFiled: May 18, 2018Date of Patent: October 19, 2021Assignee: Intel CorporationInventors: Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Tahir Ghani, Stephen M. Cea, William Hsu, Szuya S Liao, Pratik A. Patel
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Patent number: 11101268Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example.Type: GrantFiled: March 30, 2017Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Karthik Jambunathan, Scott J. Maddox, Ritesh Jhaveri, Pratik A. Patel, Szuya S. Liao, Anand S. Murthy, Tahir Ghani
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Patent number: 11090354Abstract: The present invention provides compositions and methods for treatment of metabolic syndromes. Namely, the presently disclosed compositions and methods are provided for affecting the function of the gastrointestinal endocrine system in key regions of the gut, thereby, producing therapeutic effects on obesity, diabetes and other metabolic disorders. The compositions include components for forming luminal barriers within the gastrointestinal tract of a subject where the barrier is created in-situ via interaction of resident mucin with the mucin-interacting agent.Type: GrantFiled: August 5, 2016Date of Patent: August 17, 2021Assignee: The Johns Hopkins UniversityInventors: Thomas Jozefiak, Michael Parlato, Pratik Patel, Kevin Colbert, Ashish Nimgaonkar, Pankaj Pasricha
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Patent number: 11081238Abstract: User-specific medical, genetic, fitness, environmental and nutritional data is collected to develop personalized health and wellness programs for improving a user's health and wellness. The user-specific data may be collected from medical or genetic tests, mobile health devices worn by the user and applications through which the user manually inputs information. The user-specific data is then collected and analyzed together based on knowledge of the interrelationships between medical, genetic, fitness, environmental and nutrition data to develop a comprehensive user profile and personalized health and wellness programs that are targeted to improving specific areas of the user's health by implementing changes in fitness, nutrition, medical treatment, environment, etc.Type: GrantFiled: December 20, 2017Date of Patent: August 3, 2021Assignee: MD REVOLUTION, INC.Inventors: Samir B. Damani, Vincent Valentino, Pratik Patel
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Publication number: 20210167209Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.Type: ApplicationFiled: December 2, 2019Publication date: June 3, 2021Inventors: Szuya S. LIAO, Rahul PANDEY, Rishabh MEHANDRU, Anupama BOWONDER, Pratik PATEL
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Publication number: 20210097866Abstract: Technologies for providing augmented reality wayfinding experiences in ridesharing applications are provided. In some examples, a method for providing augmented reality wayfinding experiences can include determining a first location of an autonomous vehicle (AV) relative to a second location of a client device associated with a user that requested a ride from the AV; based on the first location of the AV relative to the second location of the client device, determining a direction from the second location of the client device to the first location of the AV; presenting, at the client device, a feed from a camera sensor associated with the client device, the feed including a local scene captured by the camera sensor; and presenting a virtual content overlay on the feed, the virtual content overlay including an indication of the direction from the second location of the client device to the first location of the AV.Type: ApplicationFiled: September 30, 2019Publication date: April 1, 2021Inventors: Jessica LEARY, Jonathon STAFF, Pratik PATEL, Bradley RYAN, Josh BERLIN, John Logan ANDERSON, Michael MAGNOLI, Stanley SHIAO