Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

Abstract: Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has an upper portion and a lower epitaxial extension portion.

Abstract: An integrated circuit (IC) structure, an IC device, an IC device assembly, and a method of forming the same. The IC structure includes a transistor device on a substrate comprising: a gate structure including a metal, the gate structure on a channel structure; a source structure in a first trench at a first side of the gate structure; a drain structure in a second trench at a second side of the gate structure; a capping layer on individual ones of the source structure and of the drain structure. The capping layer comprising a semiconductor material of a same group as a semiconductor material of a corresponding one of the source structure or of the drain structure, wherein an isotope of a p-type dopant in the capping layer represents an atomic percentage of at least about 95% of a p-type isotope content of the capping layer; and metal contact structures coupled to respective ones of the source structure and of the drain structure.

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits utilizing gate plugs to induce compressive channel strain. Other embodiments may be described or claimed.

Abstract: A system configured to receive health data pertaining to a user; select a user health profile from a plurality of user health profiles based on the collected health data, each of the plurality of user health profiles being associated with a health and wellness program and a set of interventions; receive user activity data and updated health data pertaining to, or during the user's participation in the associated health and wellness program from health devices; select a new set of interventions based on the user activity data; and select a new user health profile from the plurality of user health profiles based on at least one of the user activity data and the updated health data.

Abstract: Gate-all-around integrated circuit structures having source or drain-last structures, and methods of fabricating gate-all-around integrated circuit structures having source or drain-last structures, are described. For example, a method of fabricating an integrated circuit structure includes forming a vertical arrangement of nanowires. A permanent gate stack is then formed over the vertical arrangements of nanowires. The permanent gate stack includes a high-k gate dielectric layer and a metal gate electrode. Subsequent to forming the permanent gate stack, a first epitaxial source or drain structure is formed at a first end of the vertical arrangement of nanowires, and a second epitaxial source or drain structure is formed at a second end of the vertical arrangement of nanowires.

Abstract: Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface co-planar with a top surface of the gate structure.

Abstract: Gate-all-around integrated circuit structures having source or drain structures with regrown central portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with regrown central portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.

Abstract: Gate-all-around integrated circuit structures having backside contact self-aligned to epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures.

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

Abstract: Technologies for providing real-time visualizations of a behavior of an autonomous vehicle (AV) associated with a ride request. In some examples, a method for providing real-time visualizations of a behavior of an AV associated with a ride request can include receiving a user request for a ride from an AV, wherein the user request specifies a pick-up location associated with a user; receiving sensor data from one or more sensors associated with the AV; determining, based on the sensor data, a state and context of the AV while the AV is en route to the pick-up location; and presenting, at a display interface, a map depicting one or more visual indicators of the state and context of the AV, the state and context of the AV including a location of the AV and one or more AV operations.

Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.

Abstract: A system configured to receive health data pertaining to a user; select a user health profile from a plurality of user health profiles based on the collected health data, each of the plurality of user health profiles being associated with a health and wellness program and a set of interventions; receive user activity data and updated health data pertaining to, or during the user's participation in the associated health and wellness program from health devices; select a new set of interventions based on the user activity data; and select a new user health profile from the plurality of user health profiles based on at least one of the user activity data and the updated health data.

Abstract: Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.

Abstract: Techniques are provided herein to form semiconductor devices having a different number of semiconductor nanoribbons compared to other semiconductor devices on the same substrate. In one example, two different semiconductor devices of a given memory cell, such as a random access memory (RAM) cell, include a p-channel device and an n-channel device. More specifically, the p-channel device may be a GAA transistor with a first number of semiconductor nanoribbons while the n-channel device may be a GAA transistor with a second number of semiconductor nanoribbons that is greater than the first number of semiconductor nanoribbons. In some cases, the n-channel device(s) have one additional semiconductor nanoribbon compared to the p-channel device(s). Depending on when the nanoribbons are removed during the fabrication process, different structural outcomes will occur that can be detected in the final device.

Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

Abstract: A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.