Patents by Inventor Praveen Joseph
Praveen Joseph has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240414518Abstract: Provided herein are techniques to provide per-enterprise subscriber data management (SDM) in multi-tenant network environment. In one instance, a method may include obtaining, by an SDM system, input information indicating SDM services requested for an enterprise entity in which the input information includes a multi-tenancy service attribute for the enterprise entity and indicates whether subscriber data for is to be provided on-premise for the enterprise entity. The method may further include identifying a particular SDM service of the SDM system for storing the subscriber data, deploying the particular SDM service via the SDM system, and deploying one or more on-premise SDM services at each of one or more on-premise locations of the enterprise entity for storing the subscriber data based on determining that the subscriber data is to be provided on-premise for the enterprise entity.Type: ApplicationFiled: June 6, 2023Publication date: December 12, 2024Inventors: Praveen Joseph, Timothy Peter Stammers, Monis Mohammed
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Publication number: 20240406727Abstract: Methods and systems provide authentication of signaling from on-premise network(s) to a cloud network to prevent unauthorized access to device information belonging to another enterprise/on-premise network. Methods involve a cloud proxy service obtaining a request originating from a source network function deployed in an on-premise network and destined for a destination network function deployed in a cloud network. These methods further involve determining whether the source network function is associated with an enterprise network based on a unique identifier extracted from the request. The unique identifier is indicative of a particular enterprise network.Type: ApplicationFiled: May 30, 2023Publication date: December 5, 2024Inventors: Sunil Bhambani, Praveen Joseph, Era Gupta, Kellia Surendran Suriya Ganesh, Sangeetha Shyamnath
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Publication number: 20240388938Abstract: One or more processors of a device management platform receive, from a plurality of networks, usage data indicating usage of devices on the plurality of networks. The one or more processors of the device management platform apply rules to the usage data to identify requested usage data for entities associated with the devices. The rules are defined by the entities to individually indicate the requested usage data. The one or more processors of the device management platform send the requested usage data to one or more destinations of the entities indicated by the rules.Type: ApplicationFiled: May 16, 2023Publication date: November 21, 2024Inventors: Praveen Joseph, Sunil Bhambani, Praveen Hassan Ponnappa, Kellia Surendran Suriya Ganesh
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Patent number: 12125790Abstract: Airgap isolation for back-end-of-the-line interconnect structures includes a dielectric liner formed above a top surface and opposite sidewalls of each of a plurality of metal lines on a substrate, the dielectric liner disposed above a top surface of the substrate not covered by the plurality of metal lines, portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines are separated by a space. A dielectric cap is disposed above an uppermost surface of portions of the dielectric liner above each of the plurality of metal lines and above the space, the dielectric cap pinches-off the space between portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines for providing airgaps between adjacent metal lines.Type: GrantFiled: September 29, 2021Date of Patent: October 22, 2024Assignee: International Business Machines CorporationInventors: Ashim Dutta, Ekmini Anuja De Silva, Praveen Joseph, Jennifer Church
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Publication number: 20240345082Abstract: The present disclosure provides methods for obtaining enriched populations of human red/green cone photoreceptor precursor cells with at least one of ALCAM/CD166-positive ITGA6/CD49f-negative, TNFRSF10B/CD262-negative, or NGFR/CD271-negative cell surface markers, compositions of enriched populations of human red/green cone photoreceptor precursor cells, methods for using said compositions for testing and identifying therapeutic agents specific for retinal degenerative diseases, disorders, injuries, or toxicities, and therapeutic agents specific for retinal degenerative diseases, disorders, injuries, or toxicities identified by these methods.Type: ApplicationFiled: February 26, 2024Publication date: October 17, 2024Inventors: David Gamm, Praveen Joseph Susai Manickam, Michael Phillips, Elizabeth Capowski
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Patent number: 11876136Abstract: Embodiments of the invention are directed to a semiconductor device structure that includes a first channel region over a substrate, a second channel region over the first channel region, and a merged source or drain (S/D) region over the substrate and adjacent to the first channel region and the second channel region. The merged S/D region is communicatively coupled to the first channel region and the second channel region. A wrap-around S/D contact is configured such that it is on a top surface, sidewalls, and a bottom surface of the merged S/D region.Type: GrantFiled: February 1, 2022Date of Patent: January 16, 2024Assignee: International Business Machine CorporationInventors: Yi Song, Praveen Joseph, Andrew Greene, Kangguo Cheng
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Patent number: 11864069Abstract: Techniques are described herein for network sliced based billing. In one example, a control center obtains, from a charging system, a charging data record that includes an indication of a network slice associated with a chargeable telecommunications event. Based on the indication of the network slice, the control center identifies a charging rate for the chargeable telecommunications event and applies the charging rate to the chargeable telecommunications event.Type: GrantFiled: November 3, 2020Date of Patent: January 2, 2024Assignee: CISCO TECHNOLOGY, INC.Inventors: Amit Agarwal, Rajpal Bhoria, Praveen Joseph
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Patent number: 11756961Abstract: A method includes forming a first semiconducting channel comprising a plurality of vertical nanowires and a second semiconducting channel comprising a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are formed in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are formed in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.Type: GrantFiled: January 26, 2022Date of Patent: September 12, 2023Assignee: International Business Machines CorporationInventors: Tsung-Sheng Kang, Tao Li, Ardasheir Rahman, Praveen Joseph, Indira Seshadri, Ekmini Anuja De Silva
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Patent number: 11699592Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.Type: GrantFiled: September 6, 2021Date of Patent: July 11, 2023Assignee: International Business Machines CorporationInventors: Nelson Felix, Ekmini Anuja De Silva, Praveen Joseph, Ashim Dutta
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Publication number: 20230099965Abstract: Airgap isolation for back-end-of-the-line interconnect structures includes a dielectric liner formed above a top surface and opposite sidewalls of each of a plurality of metal lines on a substrate, the dielectric liner disposed above a top surface of the substrate not covered by the plurality of metal lines, portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines are separated by a space. A dielectric cap is disposed above an uppermost surface of portions of the dielectric liner above each of the plurality of metal lines and above the space, the dielectric cap pinches-off the space between portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines for providing airgaps between adjacent metal lines.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Ashim Dutta, Ekmini Anuja De Silva, Praveen Joseph, Jennifer Church
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Patent number: 11562908Abstract: A novel dielectric cap structure for VTFET device fabrication is provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a substrate using fin hardmasks, including a first fin(s) and a second fin(s); depositing a liner over the fins and the fin hardmasks; selectively forming first hardmask caps on top of the fin hardmasks/liner over the first fin(s); forming first bottom source and drain at a base of the first fin(s) while the fin hardmasks/liner over the first fin(s) are preserved by the first hardmask caps; selectively forming second hardmask caps on top of the fin hardmasks/liner over the second fin(s); and forming second bottom source and drains at a base of the second fin(s) while the fin hardmasks/liner over the second fin(s) are preserved by the second hardmask caps. A device structure is also provided.Type: GrantFiled: April 28, 2020Date of Patent: January 24, 2023Assignee: International Business Machines CorporationInventors: Tao Li, Ekmini Anuja De Silva, Tsung-Sheng Kang, Praveen Joseph
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Patent number: 11496628Abstract: In one example, a charging filtering function may obtain a request for one or more rules that control whether or when one or more charging data records associated with a user equipment are to be provided to one or more billing systems. The request includes an identification of the user equipment. Based on the identification of the user equipment, the charging filtering function may identify the one or more rules. The charging filtering function may provide the one or more rules to control whether or when the one or more charging data records associated with the user equipment are to be provided to the one or more billing systems.Type: GrantFiled: October 2, 2020Date of Patent: November 8, 2022Assignee: CISCO TECHNOLOGY, INC.Inventors: Rajpal Bhoria, Praveen Joseph, Manoj Kumar Kushwaha, Timothy Peter Stammers
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Patent number: 11398377Abstract: A bilayer hardmask is formed on layers, the bilayer hardmask including a first hardmask layer and a second hardmask layer on the first hardmask layer. A first pattern is formed in the second hardmask layer, the first pattern including tapered sidewalls forming a first spacing in the second hardmask layer. A second pattern is formed in the first hardmask layer based on the first pattern, the second pattern comprising vertical sidewalls forming a second spacing in the first hardmask layer, the second spacing being reduced in size from the first spacing.Type: GrantFiled: January 14, 2020Date of Patent: July 26, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Praveen Joseph, Gauri Karve, Yann Mignot
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Publication number: 20220157985Abstract: Embodiments of the invention are directed to a semiconductor device structure that includes a first channel region over a substrate, a second channel region over the first channel region, and a merged source or drain (S/D) region over the substrate and adjacent to the first channel region and the second channel region. The merged S/D region is communicatively coupled to the first channel region and the second channel region. A wrap-around S/D contact is configured such that it is on a top surface, sidewalls, and a bottom surface of the merged S/D region.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Inventors: Yi Song, Praveen Joseph, Andrew Greene, Kangguo Cheng
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Publication number: 20220149042Abstract: A method includes forming a first semiconducting channel comprising a plurality of vertical nanowires and a second semiconducting channel comprising a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are formed in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are formed in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Inventors: Tsung-Sheng Kang, Tao Li, Ardasheir Rahman, Praveen Joseph, Indira Seshadri, Ekmini Anuja De Silva
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Publication number: 20220141630Abstract: Techniques are described herein for network sliced based billing. In one example, a control center obtains, from a charging system, a charging data record that includes an indication of a network slice associated with a chargeable telecommunications event. Based on the indication of the network slice, the control center identifies a charging rate for the chargeable telecommunications event and applies the charging rate to the chargeable telecommunications event.Type: ApplicationFiled: November 3, 2020Publication date: May 5, 2022Inventors: Amit Agarwal, Rajpal Bhoria, Praveen Joseph
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Patent number: 11302573Abstract: A method of forming a semiconductor structure includes forming one or more interconnect lines, the one or more interconnect lines including trenches of a first metal material surrounded by a first interlayer dielectric layer. The method also includes forming pillars of a second metal material different than the first metal material over the one or more interconnect lines utilizing a metal on metal growth process, and forming an etch stop dielectric layer, the pillars of the second metal material shaping the etch stop dielectric layer. The method further includes forming one or more vias to the one or more interconnect lines, the one or more vias being fully aligned to the one or more interconnect lines using the etch stop dielectric layer.Type: GrantFiled: October 4, 2019Date of Patent: April 12, 2022Assignee: International Business Machines CorporationInventors: Ekmini Anuja De Silva, Ashim Dutta, Praveen Joseph, Nelson Felix
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Publication number: 20220109759Abstract: In one example, a charging filtering function may obtain a request for one or more rules that control whether or when one or more charging data records associated with a user equipment are to be provided to one or more billing systems. The request includes an identification of the user equipment. Based on the identification of the user equipment, the charging filtering function may identify the one or more rules. The charging filtering function may provide the one or more rules to control whether or when the one or more charging data records associated with the user equipment are to be provided to the one or more billing systems.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Inventors: Rajpal Bhoria, Praveen Joseph, Manoj Kumar Kushwaha, Timothy Peter Stammers
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Patent number: 11296226Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. In a non-limiting example, the method includes forming a first channel region over a substrate, forming a second channel region over the first channel region, and forming a merged source or drain (S/D) region over the substrate and adjacent to the first channel region and the second channel region. The merged S/D region is communicatively coupled to the first channel region and the second channel region. A wrap-around S/D contact is formed such that it is on a top surface, sidewalls, and a bottom surface of the merged S/D region.Type: GrantFiled: October 16, 2019Date of Patent: April 5, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yi Song, Praveen Joseph, Andrew Greene, Kangguo Cheng
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Patent number: 11251182Abstract: A semiconductor structure includes a first semiconducting channel having a plurality of vertical nanowires and a second semiconducting channel having a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are configured to be in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are configured to be in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.Type: GrantFiled: March 17, 2020Date of Patent: February 15, 2022Assignee: International Business Machines CorporationInventors: Tsung-Sheng Kang, Tao Li, Ardasheir Rahman, Praveen Joseph, Indira Seshadri, Ekmini Anuja De Silva