Abstract: A method for fabricating a semiconductor device with multiple threshold voltages includes masking a substrate structure to selectively form work-function metal layers on vertical field effect transistors. In the method, a first work function metal layer is formed on a high-k dielectric layer of a substrate structure comprising vertical field effect transistors. The first work function metal layer and the high-k dielectric layer are etched to form gate regions for each vertical field effect transistor. A resist mask is formed over a first of the vertical field effect transistors. The resist mask isolates the first of the vertical field effect transistors from a second of the vertical field effect transistors. A second work function metal layer is selectively formed on the first work function metal layer of the gate region of the second of the vertical field effect transistors. The resist mask is then removed.

Abstract: Semiconductor devices and methods of forming the same include forming a first dielectric layer around a semiconductor fin, formed from a first dielectric material, to a target height lower than a height of the semiconductor fin. A second dielectric layer is deposited on the first dielectric layer and is formed from a second dielectric material. A third dielectric layer, formed from the first dielectric material, is formed on the second dielectric layer. The second dielectric layer is etched away to expose a gap on the semiconductor fin. A portion of the semiconductor fin that is exposed in the gap is oxidized to form an isolation layer.

Abstract: A technique relates to a semiconductor device. A bilayer hardmask is formed on layers, the bilayer hardmask including a first hardmask layer and a second hardmask layer on the first hardmask layer. A first pattern is formed in the second hardmask layer, the first pattern including tapered sidewalls forming a first spacing in the second hardmask layer. A second pattern is formed in the first hardmask layer based on the first pattern, the second pattern comprising vertical sidewalls forming a second spacing in the first hardmask layer, the second spacing being reduced in size from the first spacing.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. In a non-limiting example, the method includes forming a first channel region over a substrate, forming a second channel region over the first channel region, and forming a merged source or drain (S/D) region over the substrate and adjacent to the first channel region and the second channel region. The merged S/D region is communicatively coupled to the first channel region and the second channel region. A wrap-around S/D contact is formed such that it is on a top surface, sidewalls, and a bottom surface of the merged S/D region.

Abstract: A method of forming a semiconductor structure includes forming one or more interconnect lines, the one or more interconnect lines including trenches of a first metal material surrounded by a first interlayer dielectric layer. The method also includes forming pillars of a second metal material different than the first metal material over the one or more interconnect lines utilizing a metal on metal growth process, and forming an etch stop dielectric layer, the pillars of the second metal material shaping the etch stop dielectric layer. The method further includes forming one or more vias to the one or more interconnect lines, the one or more vias being fully aligned to the one or more interconnect lines using the etch stop dielectric layer.

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

Abstract: Semiconductor devices and methods of forming the same include forming a first dielectric layer around a semiconductor fin, formed from a first dielectric material, to a target height lower than a height of the semiconductor fin. A second dielectric layer is deposited on the first dielectric layer and is formed from a second dielectric material. A third dielectric layer, formed from the first dielectric material, is formed on the second dielectric layer. The second dielectric layer is etched away to expose a gap on the semiconductor fin. A portion of the semiconductor fin that is exposed in the gap is oxidized to form an isolation layer.

Abstract: A MRAM-TFT unit cell and a method for fabricating the same. The MRAM-TFT unit cell includes a MRAM device and a TFT device electrically coupled to the MRAM device. The MRAM device and the TFT device are situated within a common plane of the MRAM-TFT cell. The method includes forming a TFT device comprising a source/drain region, and a semiconducting layer on a substrate. A magnetic tunnel junction stack (MTJ) is formed in contact with the source region. A first contact is formed on the MTJ, and a second contact is formed on the drain region. A first interconnect metal layer is formed in contact with the first contact, and a second first interconnect metal layer is formed in contact with the second contact. A third contact is formed on a gate region of the TFT device. A third interconnect metal layer is formed in contact with the third contact.

Abstract: A method for fabricating a semiconductor device with multiple threshold voltages includes masking a substrate structure to selectively form work-function metal layers on vertical field effect transistors. In the method, a first work function metal layer is formed on a high-k dielectric layer of a substrate structure comprising vertical field effect transistors. The first work function metal layer and the high-k dielectric layer are etched to form gate regions for each vertical field effect transistor. A resist mask is formed over a first of the vertical field effect transistors. The resist mask isolates the first of the vertical field effect transistors from a second of the vertical field effect transistors. A second work function metal layer is selectively formed on the first work function metal layer of the gate region of the second of the vertical field effect transistors. The resist mask is then removed.

Abstract: A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.

Abstract: Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.

Abstract: Techniques regarding the replenishment of one or more hard mask layers to facilitate one or more etching processes are provided. For example, one or more embodiments described herein can comprise a method, which can comprise replenishing an oxide layer onto a surface of a semiconductor substrate by thermally oxidizing the surface of the semiconductor substrate. The oxide layer can facilitate selective etching of the semiconductor substrate.

Abstract: A method of preventing the collapse of fin structures is provided. The method includes forming a plurality of vertical fins on a substrate, and a hard mask stack on each of the vertical fins. The method further includes forming a cover layer on the plurality of vertical fins and hard mask stacks, and reducing the height of the cover layer to expose an upper portion of each of the hard mask stacks. The method further includes forming a bracing layer on the reduced height cover layer and exposed portion of each of the hard mask stacks, and removing a portion of the bracing layer to expose a portion of the reduced height cover layer and form a bracing segment on the exposed portion of each of the hard mask stacks. The method further includes removing the reduced height cover layer.

Abstract: A MRAM-TFT unit cell and a method for fabricating the same. The MRAM-TFT unit cell includes a MRAM device and a TFT device electrically coupled to the MRAM device. The MRAM device and the TFT device are situated within a common plane of the MRAM-TFT cell. The method includes forming a TFT device comprising a source/drain region, and a semiconducting layer on a substrate. A magnetic tunnel junction stack (MTJ) is formed in contact with the source region. A first contact is formed on the MTJ, and a second contact is formed on the drain region. A first interconnect metal layer is formed in contact with the first contact, and a second first interconnect metal layer is formed in contact with the second contact. A third contact is formed on a gate region of the TFT device. A third interconnect metal layer is formed in contact with the third contact.

Abstract: A method for fabricating a semiconductor device with multiple threshold voltages includes masking a substrate structure to selectively form work-function metal layers on vertical field effect transistors. In the method, a first work function metal layer is formed on a high-k dielectric layer of a substrate structure comprising vertical field effect transistors. The first work function metal layer and the high-k dielectric layer are etched to form gate regions for each vertical field effect transistor. A resist mask is formed over a first of the vertical field effect transistors. The resist mask isolates the first of the vertical field effect transistors from a second of the vertical field effect transistors. A second work function metal layer is selectively formed on the first work function metal layer of the gate region of the second of the vertical field effect transistors. The resist mask is then removed.

Abstract: A method for fabricating a semiconductor device with multiple threshold voltages includes masking a substrate structure to selectively form work-function metal layers on vertical field effect transistors. In the method, a first work function metal layer is formed on a high-k dielectric layer of a substrate structure comprising vertical field effect transistors. The first work function metal layer and the high-k dielectric layer are etched to form gate regions for each vertical field effect transistor. A resist mask is formed over a first of the vertical field effect transistors. The resist mask isolates the first of the vertical field effect transistors from a second of the vertical field effect transistors. A second work function metal layer is selectively formed on the first work function metal layer of the gate region of the second of the vertical field effect transistors. The resist mask is then removed.

Abstract: A method of preventing the collapse of fin structures is provided. The method includes forming a plurality of vertical fins on a substrate, and a hard mask stack on each of the vertical fins. The method further includes forming a cover layer on the plurality of vertical fins and hard mask stacks, and reducing the height of the cover layer to expose an upper portion of each of the hard mask stacks. The method further includes forming a bracing layer on the reduced height cover layer and exposed portion of each of the hard mask stacks, and removing a portion of the bracing layer to expose a portion of the reduced height cover layer and form a bracing segment on the exposed portion of each of the hard mask stacks. The method further includes removing the reduced height cover layer.

Abstract: A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.

Abstract: Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.

Abstract: Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.