Abstract: A method includes receiving, at a user identification module of an electronic receipt system in electronic communication with a point of sale terminal, a user identifier transmitted from a mobile communication device to a near-field communication enabled communication device associated with the point of sale terminal. The method also includes verifying, by a validation module of the electronic receipt system, an enrollment status of the user identifier; and based on results of the verifying, transmitting, by a transfer module of the electronic receipt system, the user identifier and data characterizing an electronic receipt to a receipt storage module of the electronic receipt system.

Abstract: Method and computer program product for using an RFID antenna of a cooking appliance to read a plurality of cooking instruction sets from a single RFID tag associated with a food product that is positioned to be cooked by the cooking appliance. The cooking appliance selects one of the plurality of cooking instruction sets that the cooking appliance is capable of performing. Furthermore, the cooking appliance may then automatically cook the food product by controlling the cooking appliance according to the selected cooking instruction set. The selection of a cooking instruction set may consider the temperature of the food product or a determination whether the food product is frozen. Alternatively, cooking appliance settings may be interpolated between two cooking instruction sets or calculated on the basis of physical property information about the food product.

Abstract: A multijunction solar cell having at least four solar subcells includes a first solar subcell having a first band gap, and a first graded interlayer adjacent to the first solar subcell, wherein the first graded interlayer has a second band gap greater than the first band gap and that is constant at 1.5 eV throughout the thickness of the first graded interlayer. A second solar subcell is adjacent to the first graded interlayer, wherein the second solar subcell has a third band gap smaller than the first band gap of the first solar subcell and wherein said second solar subcell is lattice mismatched with respect to the first solar subcell. A second graded interlayer is adjacent to the second solar subcell, wherein the second graded interlayer has a fourth band gap greater than the third band gap of the second solar subcell and that is constant at 1.1 eV throughout the thickness of the second graded interlayer.

Abstract: A method includes receiving, at a user identification module of an electronic receipt system in electronic communication with a point of sale terminal, a user identifier transmitted from a mobile communication device to a near-field communication enabled communication device associated with the point of sale terminal. The method also includes verifying, by a validation module of the electronic receipt system, an enrollment status of the user identifier; and based on results of the verifying, transmitting, by a transfer module of the electronic receipt system, the user identifier and data characterizing an electronic receipt to a receipt storage module of the electronic receipt system.

Abstract: A photovoltaic solar cell for producing energy from the sun including a germanium substrate including a first photoactive junction and forming a bottom solar subcell; a gallium arsenide middle cell disposed on said substrate; an indium gallium phosphide top cell disposed over the middle cell; and a surface grid including a plurality of spaced apart grid lines, wherein the grid lines have a thickness greater than 7 microns, and each grid line has a cross-section in the shape of a trapezoid with a cross-sectional area between 45 and 55 square microns.

Abstract: A linear regulator integrated circuit may be formed having four external terminals including a voltage input (Vin) terminal, a voltage output (Vout) terminal, a Set terminal, and an operational amplifier (op amp) power terminal. A user connects an external resistor to the Set terminal for creating a reference voltage. An op amp controls a pass (or series transistor) to cause an output voltage at the Vout terminal to equal the reference voltage. The op amp has a first power supply terminal internally coupled to the Vin terminal and a second power supply terminal coupled to the op amp power terminal. The op amp power terminal allows a user to externally couple the op amp second power supply terminal to either the Vout pin (for high voltage applications), system ground (for medium voltage applications), or another voltage (to provide additional headroom in very low voltage applications).

Abstract: A multijunction solar cell including an upper first solar subcell, and the base-emitter junction of the upper first solar subcell being a homojunction; a second solar subcell adjacent to said first solar subcell; a third solar subcell adjacent to said second solar subcell. A first graded interlayer is provided adjacent to said third solar subcell. A fourth solar subcell is provided adjacent to said first graded interlayer, said fourth subcell is lattice mismatched with respect to said third subcell. A second graded interlayer is provided adjacent to said fourth solar subcell; and a lower fifth solar subcell is provided adjacent to said second graded interlayer, said lower fifth subcell is lattice mismatched with respect to said fourth subcell.

Abstract: A solar cell array includes multiple cells connected to one another in series on a surface. The array includes first and second different types of solar cells. Incorporating two different types of cells can facilitate various layouts of the cells in the array, including compact arrangements. In some implementations, the use of two different types of cells can allow arrangements in which voltage terminals of opposite polarity to be disposed at a sufficiently large distance from one another so as to help reduce the occurrence of ESD.

Abstract: A linear regulator contains an additional AC-coupled feedback loop between the output of the error amplifier and the base of the pass transistor that increases the frequency of the pole at the output of the error amplifier at light load currents to at least partially offset the decreased frequency of the output pole at the lighter load currents. Thus, a desired phase margin is preserved. The AC-coupled feedback loop includes a bipolar feedback transistor connected in parallel with the pass transistor. A resistor is connected to the emitter of the feedback transistor to reduce the relative gain of the feedback transistor above light load currents. A feedback capacitor Cfb is connected between the collector of the feedback transistor and the output of the error amplifier. The negative AC feedback increases the pole frequency at the output of the error amplifier and the base of the pass transistor.

Abstract: A method of forming a multijunction solar cell comprising at least an upper subcell, a middle subcell, and a lower subcell, the method including forming a first alpha layer over said middle solar subcell using a surfactant and dopant including selenium, the first alpha layer configured to prevent threading dislocations from propagating; forming a metamorphic grading interlayer over and directly adjacent to said first alpha layer; forming a second alpha layer using a surfactant and dopant including selenium over and directly adjacent to said grading interlayer to prevent threading dislocations from propagating; and forming a lower solar subcell over said grading interlayer such that said lower solar subcell is lattice mismatched with respect to said middle solar subcell.

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract: A linear regulator contains an additional AC-coupled feedback loop between the output of the error amplifier and the base of the pass transistor that increases the frequency of the pole at the output of the error amplifier at light load currents to at least partially offset the decreased frequency of the output pole at the lighter load currents. Thus, a desired phase margin is preserved. The AC-coupled feedback loop includes a bipolar feedback transistor connected in parallel with the pass transistor. A resistor is connected to the emitter of the feedback transistor to reduce the relative gain of the feedback transistor above light load currents. A feedback capacitor Cfb is connected between the collector of the feedback transistor and the output of the error amplifier. The negative AC feedback increases the pole frequency at the output of the error amplifier and the base of the pass transistor.

Abstract: In one embodiment, a regulator circuit for generating a regulated output voltage Vout has an error amplifier using a pair of bipolar transistors at its front end. The error amplifier compares the regulated output voltage to a reference voltage Vref. A precision current source draws a first current through a user-selected set resistance to generate the desired Vref. The regulator circuit controls a power stage to cause Vout to be equal to Vref. The base current into one of the bipolar transistors normally distorts the current through the set resistance. A base current compensation circuit is coupled to the current source to adjust the first current by a value equal to the base current to offset the base current. Therefore, Vref is not affected by the base current. The error amplifier may be in a linear regulator or a switching regulator. The compensation circuit may be used in other applications.

Abstract: A linear regulator integrated circuit may be formed having four external terminals including a voltage input (Vin) terminal, a voltage output (Vout) terminal, a Set terminal, and an operational amplifier (op amp) power terminal. A user connects an external resistor to the Set terminal for creating a reference voltage. An op amp controls a pass (or series transistor) to cause an output voltage at the Vout terminal to equal the reference voltage. The op amp has a first power supply terminal internally coupled to the Vin terminal and a second power supply terminal coupled to the op amp power terminal. The op amp power terminal allows a user to externally couple the op amp second power supply terminal to either the Vout pin (for high voltage applications), system ground (for medium voltage applications), or another voltage (to provide additional headroom in very low voltage applications).

Abstract: A multijunction photovoltaic cell including a top subcell; a second subcell disposed immediately adjacent to the top subcell and producing a first photo-generated current; and including a sequence of first and second different semiconductor layers with different lattice constant; and a lower subcell disposed immediately adjacent to the second subcell and producing a second photo-generated current substantially equal in amount to the first photo-generated current density.

Abstract: A solar cell interconnect assembly and a method for manufacturing the same are provided. In an embodiment, the method may include: providing a solar cell having an interconnect member formed thereon, the interconnect member comprising a metallic part formed on a surface of the solar cell and a first precursor layer formed over the metallic part; providing an interconnector comprising a second precursor layer at a surface thereof; heating the interconnector and the interconnect member to a temperature equal to or above a eutectic temperature of the materials of the first and second precursor layers and pressing one of them against the other so as to form a eutectic liquid phase; and isothermal solidifying the eutectic liquid to form a bonding layer of eutectic alloy.

Abstract: The present invention in a preferred embodiment provides systems and methods for facilitation of recruitment or hiring on an online interface which provide the employer with the “jobseekers' search list” based on a predefined questionnaire or custom questionnaire comprising of direct questions or queries or multiple choice options, whereby any descriptive or elaborate answers or details are eliminated. Jobseekers' attributes are matched with employers' desired job attributes based on the predefined questionnaire or custom questionnaires. Matching of the attributes generates scores or ranks depending on a pre-defined system and weightage provided to specific job attributes.

Abstract: A multijunction solar cell including a first solar subcell having a first band gap and a first short-circuit current; a second solar subcell disposed over the first solar subcell and having a second band gap greater than the first band gap and a second short-circuit current greater than the first short-circuit current by an amount in the range of 2% to 6%; a third solar subcell disposed over the second solar subcell and having a third band gap greater than the second band gap and a third short-circuit current less than the first short-circuit current by an amount in the range of 2% to 6%; and a fourth solar subcell disposed over the third solar subcell having a fourth band gap greater than the third band gap, and a fourth short-circuit current less than the third short-circuit current by an amount in the range of 6% to 10%, so that at an “end of life” state of the multijunction solar cell in an AM0 space environment the short-circuit current of each of the subcells are substantially identical.

Abstract: A multijunction solar cell for a space radiation environment, the multijunction solar cell having a plurality of solar sub-cells arranged in order of decreasing band gap including: a first solar subcell composed of InGaP and having a first band gap, the first solar subcell having a first short circuit current associated therewith; a second solar subcell composed of GaAs and having a second band gap which is less than the first band gap, the second solar subcell having a second short circuit current associated therewith; wherein in a beginning of life state the first short circuit current is less than the second short circuit current such that the AM0 conversion efficiency is sub-optimal. However, in an end of life state, the short circuit current are substantially matched, which results in an improved AM0 conversion efficiency.

Abstract: Methods and systems for implementing such methods for providing server fault notifications, diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node. The displaying of the diagnostic service notifications may allow for the completion of various service operations associated with the service notifications once the information specific to a fault is presented.