Abstract: A method for debugging client-side code includes a client receiving an application file set from a server in response to the client requesting an application. A singleton is generated on the client by executing a script in the application file set. The singleton monitors a data event generated by an application programming interface. The singleton writes a client data record to a cache memory in response to the application programming interface generating the data event. The client data record records an application event. The singleton flushes the contents of the cached memory in response to a flush event, and transfers the contents to the server for persistent storage.

Abstract: The invention, which may be a kind of annotations processor, detects zero or more tagsets turned on or selected at runtime. The annotations adapter reads an abstract unit from a java file, and if an annotation of the abstract unit has a tag that is among the tags of a turned on tagset, then the annotations adapter may generate an artifact showing the influence of the annotation. Such a process may continue until there are no more abstract units to process. Comments or annotations that fail to be tagged with a tag of a selected tagset may, nevertheless, be mentioned with a kind of ‘place-holder’ indicating that such comments exist.

Abstract: A photovoltaic solar cell for producing energy from the sun including a germanium substrate including a first photoactive junction and forming a bottom solar subcell; a gallium arsenide middle cell disposed on said substrate; an indium gallium phosphide top cell disposed over the middle cell; and a surface grid including a plurality of spaced apart grid lines, wherein the grid lines have a thickness greater than 7 microns, and each grid line has a cross-section in the shape of a trapezoid with a cross-sectional area between 45 and 55 square microns.

Abstract: In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem.

Abstract: Methods and systems for implementing such methods for providing server diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node. Display of diagnostic service notifications may allow for completion of various service operations associated with service notifications once information specific to a fault is presented. Such service operations may include placing a system in standby mode, transferring workloads to other systems, initiating a firmware update, placing the system in a mode that allows for physical maintenance, or ordering parts associated with one or more faults.

Abstract: A multijunction solar cell including an upper first solar subcell, and the base-emitter junction of the upper first solar subcell being a homojunction; a second solar subcell adjacent to said first solar subcell; a third solar subcell adjacent to said second solar subcell. A first graded interlayer is provided adjacent to said third solar subcell. A fourth solar subcell is provided adjacent to said first graded interlayer, said fourth subcell is lattice mismatched with respect to said third subcell. A second graded interlayer is provided adjacent to said fourth solar subcell; and a lower fifth solar subcell is provided adjacent to said second graded interlayer, said lower fifth subcell is lattice mismatched with respect to said fourth subcell.

Abstract: Methods and systems for implementing such methods for providing server fault notifications, diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node. The displaying of the diagnostic service notifications may allow for the completion of various service operations associated with the service notifications once the information specific to a fault is presented.

Abstract: According to one embodiment, an apparatus has first and second connectors configured for removably connecting to one another. The first connector circuit has a first differential amplifier, a first differential signal path, a first capacitor section capacitively coupling the first differential amplifier to the first differential signal path, and a first DC biasing circuit for imparting a first DC bias to the first differential signal path opposite the first capacitor section. The second connector circuit has a second differential amplifier, a second differential signal path, a second capacitor section capacitively coupling the second differential amplifier to the second differential signal path, and a second DC biasing circuit for imparting a second DC bias to the second differential signal path opposite the second capacitor section having a different magnitude than the first DC bias when the first and second connector are not connected.

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract: Methods and apparatus for workload balancing among power switching components in a multiphase switching power supply, the power supply including one set of power switching components for each switching phase, where workload balancing includes: dropping one or more switching phases when output current demand on the power supply drops below a predetermined threshold, leaving at least one active switching phase; and rotating the at least one active switching phase among all sets of power switching components.

Abstract: A system for allowing a designer to implement Universal Serial Bus (USB) 2.0 in topologies not anticipated by a USB 2.0 specification and with reduced channel losses, the system comprising: a bus channel having a plurality of electrical elements; and a boost circuit connected at a predetermined location on the bus channel; a plurality of USB signals transmitted through the system; wherein edges of the plurality of USB signals are boosted without impacting the bi-directional nature of the bus channel.

Abstract: A method includes receiving, at a user identification module of an electronic receipt system in electronic communication with a point of sale terminal, a user identifier transmitted from a mobile communication device to a near-field communication enabled communication device associated with the point of sale terminal. The method also includes verifying, by a validation module of the electronic receipt system, an enrollment status of the user identifier; and based on results of the verifying, transmitting, by a transfer module of the electronic receipt system, the user identifier and data characterizing an electronic receipt to a receipt storage module of the electronic receipt system.

Abstract: Testing an electrical component, the component including a printed circuit board (‘PCB’) with a number of traces, the traces organized in pairs with each trace of a pair carrying current in opposite directions and separated from one another by a substrate layer of the PCB, where testing of the electrical component includes: dynamically and iteratively until a present impedance for a pair of traces of the component is greater than a predetermined threshold impedance: increasing, by an impedance varying device at the behest of a testing device, magnetic field strength of a magnetic field applied to the pair of traces by the impedance varying device, including increasing the present impedance of the pair of traces; measuring, by the testing device, one or more operating parameters; and recording, by the testing device, the measurements of the operating parameters.

Abstract: A printed circuit board (‘PCB’) with a capacitor integrated within a via of the PCB, the PCB including layers of laminate; a via that includes a via hole traversing layers of the PCB, the via hole characterized by a generally tubular inner surface; a capacitor integrated within the via, the capacitor including two capacitor plates, an inner plate and an outer plate, the two plates composed of electrically conductive material disposed upon the inner surface of the via hole, both plates traversing layers of the laminate, the inner plate traversing more layers of the laminate than are traversed by the outer plate; and a layer of dielectric material disposed between the two plates.

Abstract: Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time.

Abstract: An integrated circuit (IC) that includes a semiconductor die in an IC package. The semiconductor die includes an electrical endpoint. The IC also includes a pad affixed to the semiconductor die. The pad is characterized by a capacitance and is coupled to the electrical endpoint. The IC also includes a bond wire coupling the pad to an IC package pin. The bond wire is an inductor characterized by an inductance. The inductance is configured to decrease signal degradation caused by the capacitance of the pad on electrical signals transmitted between the pin and the electrical endpoint of the semiconductor die.

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract: Settings are provided by a chassis management controller to an expansion card in a multi-slot server chassis. The chassis management controller in a multi-slot server chassis provides an operating parameter to a server management controller in a server, and the server management controller writes the operating parameter to a port expander of an expansion card installed on the server. The operating parameter is written to the port expander prior to expansion card power up, and the expansion card uses the operating parameter after power up to derive one or more SERDES value. The SERDES value is used to program an ASIC chip comprising a SERDES converter on the expansion card. In one example, the operating parameter is determined by the capabilities of a chassis midplane at the slot where the compute node is installed.

Abstract: Embodiments of the invention include a common mode cancellation circuit and method for correcting signal skew in a differential circuit. According to one embodiment, an op amp circuit is used to correct the mismatch between transmission line lengths in the differential circuit. The CMCC can be embodied as an ASIC and added on to an existing differential signaling systems to correct and compensate for board wiring skew or other causes of phase misalignment. The result is restoration of the cross-over intersection of the plus and minus signals of the differential pair closer to the common voltage level point, as if the signals had been in phase.