Patents by Inventor Pu Wang

Pu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12639612
    Abstract: Communication-capable devices such as commercial Wi-Fi devices can be used for integrated sensing and communications (ISAC) systems to jointly exchange data and monitor environment. Such devices typically require diverse signal processing such as machine learning inference that demands high-power operations for real-time sensing and computing. The present invention provides a way to realize energy-efficient computing by exploiting the capability of data communications to access distributed computing resources including classical computers and quantum computers over networks. The system and method are based on the realization that computationally intensive processing is offloaded to networked hybrid classical-quantum computing to build dynamic computing graphs. Some embodiments use automated classical-quantum machine learning whose circuits and hyperparameters are automatically adjusted via gradient or heuristic optimization for Wi-Fi indoor monitoring and human tracking.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: May 26, 2026
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Toshiaki Koike Akino, Ye Wang, Pu Wang
  • Patent number: 12642086
    Abstract: A method includes placing a package, which includes a first package component, a second package component, and an encapsulant encapsulating the first package component and the second package component therein. The method further includes attaching a first thermal interface material over the first package component, attaching a second thermal interface material different from the first thermal interface material over the second package component, and attaching a heat sink over both of the first thermal interface material and the second thermal interface material.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: May 26, 2026
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 12631241
    Abstract: The present invention relates to an electric drum, which comprises a dual-gear reduction mechanism that comprises at least one stage of sun dual-gear, N planetary dual-gear sets and a gear ring; the at least one stage of sun dual-gear is coaxially arranged with an output gear shaft of a motor; the N planetary dual-gear sets surround the at least one stage of sun dual-gear, and the structure of each planetary dual-gear set comprises a planetary pin, on which at least one stage of planetary dual-gears and an output planetary gear are sequentially sleeved in an axial direction; two ends of the planetary pin are fixedly connected with fixing parts in the drum body; the various stages of sun dual-gears are sequentially engaged with the planetary dual-gears, and finally the drum body is driven to rotate via the engagement between the output planetary gear and the gear ring; the N planetary dual-gears in each stage are evenly distributed around the sun dual-gear, and N is greater than or equal to 3.
    Type: Grant
    Filed: April 2, 2025
    Date of Patent: May 19, 2026
    Assignee: Jiangsu Winroller Transmission Technology Co., LTD
    Inventors: Pu Wang, Xinjun Xue
  • Publication number: 20260136935
    Abstract: A package structure includes a package substrate, a semiconductor module on the package substrate, a package lid on the semiconductor module and attached to the package substrate, and a hybrid thermal interface material (TIM) structure between the semiconductor module and the package lid, including a TIM layer and a vapor core heat spreader in the TIM layer.
    Type: Application
    Filed: November 11, 2024
    Publication date: May 14, 2026
    Inventors: Yi-Huan Liao, Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
  • Publication number: 20260130209
    Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the semiconductor package via the thermal conductive bonding layer. The lid has a first cavity and a second cavity connected to the first cavity. The semiconductor package is located in the first cavity, and the thermal conductive bonding layer is partially disposed in the second cavity. The second cavity has a first portion and a second portion joined with the first portion and narrower than the first portion, the second portion is located between the first portion and the first cavity, and the thermal conductive bonding layer is formed in the second portion. A method for manufacturing a semiconductor device is also provided.
    Type: Application
    Filed: November 4, 2024
    Publication date: May 7, 2026
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Liao, Po-Yuan Cheng, Chih-Hao Chen, Pu Wang, Li-Hui Cheng
  • Publication number: 20260098939
    Abstract: The present disclosure provides a system and a method for perceiving an object in a scene. The method comprises collecting features of a first radar image of the scene captured from a first sensor and a second radar image of the scene captured from a second sensor, each of the first radar image and the second radar image includes depth data. The method further comprises processing selected features of the collected features with a transformer neural network having a transformer architecture with self-attention over the selected features and cross-attention between object queries and the selected features to produce 2D+ embeddings of the object. The method further comprises processing the 2D+ embeddings with a detection neural network to perceive the object and produce an image of the scene with markings of the perceived object, and outputting the image of the scene with the markings of the perceived object.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 9, 2026
    Applicant: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Pu Wang, Ryoma Yataka, Adriano Cardace, Petros Boufounos
  • Publication number: 20260092527
    Abstract: An intelligent automatic coal powder receiving device based on prevention and control of rock burst in coal mines includes a driving vehicle. Wheels with a moving function and a central processor are set on the driving vehicle, supporting mechanisms are set symmetrically on both sides of the driving vehicle, a coal powder storage box and a cross double frame positioning mechanism are set at the top of the driving vehicle, a coal powder receiving pipe is set on the cross double frame positioning mechanism, a binocular camera is set at the coal powder receiving pipe, and one end of the coal powder receiving pipe is a coal powder inlet, the other end of the coal powder receiving pipe is connected to the coal powder storage box through a connecting pipe, and the cross double frame positioning mechanism is connected to the driving vehicle through a telescopic mechanism.
    Type: Application
    Filed: December 3, 2024
    Publication date: April 2, 2026
    Applicant: Shandong University of Science and Technology
    Inventors: Pu WANG, Mei ZHANG, Chuanyang ZHANG, Zesheng WEI, Huidan CHEN
  • Patent number: 12585450
    Abstract: A network manager for delivering a firmware/software program to multi-mode nodes and single-mode nodes arranged in a multi-hop wireless IoT network. The network manager includes a transceiver configured to perform wireless communication by transmitting the encoded packets of the firmware/software program to the first-hop nodes. The network manager divides firmware/software program into source blocks, encodes the source blocks into encoded blocks based on coding scheme, packs the encoded blocks into encoded packets, and transmits the encoded packets to the first-hop nodes. The first-hop nodes may be configured to receive, decode, re-encode and re-transmit the encoded packets. The network manager keeps broadcasting the encoded packets to the first-hop nodes until a predetermined percent of the first-hop nodes receive the firmware/software program.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: March 24, 2026
    Assignees: Mitsubishi Electric Research Laboratories, Inc., Mitsubishi Electric Corporation
    Inventors: Jianlin Guo, Jothi Prasanna Shanmuga Sundaram, Toshiaki Koike Akino, Pu Wang, Kieran Parsons, Philip Orlik, Takenori Sumi, Yukimasa Nagai
  • Patent number: 12572815
    Abstract: The present disclosure provides a method and a system for training a neural network suitable for localization of a device within an environment based on signals received by the device. The method comprises training a bi-regressor neural network to identify locations from labeled data, wherein the bi-regressor neural network includes a feature extractor and a bi-regressor including two regressors; training parameters of the bi-regressor using the labeled data and unlabeled data, such that each of the two regressors identifies the same labeled locations while processing the labeled data and identifies different locations while processing the unlabeled data; and training parameters of the feature extractor using an adversarial discriminator to extract domain invariant features from the unlabeled data with statistical properties of the labeled data according to the adversarial discriminator such that each of the two regressors identifies the same locations while processing the domain invariant features.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: March 10, 2026
    Inventors: Pu Wang, Haifeng Xia, Toshiaki Koike Akino, Ye Wang, Philip Orlik
  • Publication number: 20260065565
    Abstract: A computer-implemented method includes converting by a pose tokenizer, based on a learned codebook, pose parameters of a body into a sequence of discrete pose tokens; randomly masking a portion of the sequence of discrete pose tokens; predicting the randomly masked sequence of discrete pose tokens based on multi-scale features extracted from a monocular image by an image conditioned masked transformer; optimizing the sequence of discrete pose tokens by aligning a re-projected three-dimensional (3D) pose with an estimated two-dimensional (2D) pose; directly regressing, from the multi-scale features, a shape parameter of the body and a weak perspective camera parameter; and generating a 3D mesh reconstruction of the body based on the shape parameter and the weak perspective camera parameter.
    Type: Application
    Filed: September 4, 2025
    Publication date: March 5, 2026
    Inventors: Pu Wang, Muhammad Usama Saleem, Ekkasit Pinyoanuntapong, Parshwa Shah, Foram Shah
  • Publication number: 20260068750
    Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.
    Type: Application
    Filed: November 6, 2025
    Publication date: March 5, 2026
    Inventors: Yi-Huan Liao, Ping-Yin Hsieh, Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Patent number: 12494401
    Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: December 9, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Huan Liao, Ping-Yin Hsieh, Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20250364355
    Abstract: A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) structure, and a lid structure. The package structure is disposed on the substrate. The TIM structure is disposed on the package structure. The TIM structure includes a metallic TIM layer and a non-metallic TIM layer in contact with the metallic TIM layer, and the non-metallic TIM layer surrounds the metallic TIM layer. The lid structure is disposed on the substrate and the TIM structure.
    Type: Application
    Filed: August 4, 2025
    Publication date: November 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chih Chiou, Ping-Yin Hsieh, Ying-Ching Shih, Pu Wang, Li-Hui Cheng, Yi-Huan Liao, Chih-Hao Chen
  • Publication number: 20250357366
    Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip structure over a substrate. The method includes forming an adhesive wall structure over the substrate and surrounding the chip structure. The adhesive wall structure has a convex curved sidewall facing away from the chip structure. The method includes forming an adhesive layer over the substrate. The adhesive layer surrounds the adhesive wall structure, and a first Young's modulus of the adhesive layer is different from a second Young's modulus of the adhesive wall structure. The method includes disposing a heat-spreading lid over the adhesive layer to cover the adhesive wall structure and the chip structure. The heat-spreading lid is bonded to the adhesive layer and the adhesive wall structure.
    Type: Application
    Filed: May 20, 2024
    Publication date: November 20, 2025
    Inventors: Hung-Yu CHEN, Pu WANG, Li-Hui CHENG
  • Publication number: 20250357260
    Abstract: A package structure is provided. The package structure includes a substrate, a die bonded to the substrate, a lid disposed over the die and the substrate, and an interface structure sandwiched between the die and the lid and including a first thermal interface material disposed at corners of a top surface of the die, and a second thermal interface material disposed a rest of the top surface of the die. A Young's modulus of the first thermal interface material is smaller than a Young's modulus of the second thermal interface material.
    Type: Application
    Filed: July 25, 2025
    Publication date: November 20, 2025
    Inventors: Chun-Yen Lan, Yu-Hsun Wang, Pu Wang, Li-Hui Cheng, Ying-Ching Shih, Yu-Wei Lin
  • Publication number: 20250349797
    Abstract: Embodiments of the present disclosure provide a package structure. The package structure includes a semiconductor die. An underfill material is below the semiconductor die and extends up to a sidewall of the semiconductor die. A molding compound surrounds the semiconductor die and the underfill material. An interface material is between the molding compound and the underfill material.
    Type: Application
    Filed: May 8, 2024
    Publication date: November 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chien PAN, Pu WANG, Li-Hui CHENG
  • Publication number: 20250349658
    Abstract: A package structure is provided. The package structure includes a substrate, a package component bonded to the substrate, a lid disposed over the package component and the substrate, and an interface structure sandwiched between the package component. The package component includes a first die, a second die laterally spaced apart from the first die by an underfill, and a molding compound adjacent the first die and the second die. The interface structure includes an adhesive layer disposed over the underfill and the molding compound, and a thermal interface material (TIM) layer over the adhesive layer, the first die and the second die.
    Type: Application
    Filed: July 24, 2025
    Publication date: November 13, 2025
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng
  • Publication number: 20250349654
    Abstract: The present disclosure provides a method. In some embodiments, the method includes providing a substrate; bonding a package structure to the substrate; attaching a ring structure on the substrate and surrounding the package structure; forming a thermal interface material (TIM) layer over the package structure; attaching a heat sink structure to the TIM layer and the ring structure.
    Type: Application
    Filed: May 9, 2024
    Publication date: November 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin HSIEH, Pu WANG, Li-Hui CHENG
  • Publication number: 20250349629
    Abstract: A package structure includes a substrate. A package is over the substrate. A contour ring is mounted over the substrate, in which the contour ring surrounds the package and has an opening. A top lid is mounted over the contour ring, in which the top lid has a portion extending into the opening of the contour ring.
    Type: Application
    Filed: May 9, 2024
    Publication date: November 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chien PAN, Chun-Yen LAN, Pu WANG, Li-Hui CHENG, Ying-Ching SHIH
  • Publication number: 20250343166
    Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip structure over the wiring substrate. The chip package structure includes a first ring structure over the wiring substrate and surrounding the chip structure, wherein a first coefficient of thermal expansion of the first ring structure is less than a second coefficient of thermal expansion of the wiring substrate. The chip package structure includes an anti-warpage structure over the first ring structure. A third coefficient of thermal expansion of the anti-warpage structure is greater than the first coefficient of thermal expansion of the first ring structure.
    Type: Application
    Filed: July 14, 2025
    Publication date: November 6, 2025
    Inventors: Chun-Yen Lan, Yu-Hsun Wang, Pu Wang, Li-Hui Cheng, Ying-Ching Shih