Patents by Inventor Pu Wang

Pu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260334329
    Abstract: A package structure includes a lower package including a first semiconductor die including a backside metal film on a backside of the first semiconductor die, an upper package attached to the lower package and electrically coupled to the lower package, and a thermally conductive underfill layer between the lower package and the upper package and contacting the backside metal film.
    Type: Application
    Filed: July 3, 2026
    Publication date: October 22, 2026
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20260324422
    Abstract: A method of manufacturing a thermal interface material comprising forming a stack of alternating layers of a first component and a second component stacked along a first direction such that interfaces between adjacent alternating layers are perpendicular to the first direction and extend along a second direction and a third direction, performing a compression operation to compress the stack of alternating layers so that adjacent layers adhere to one another to form a bulk thermal interface material, and slicing the bulk thermal interface material along planes perpendicular to the first direction, the second direction, and the third direction to generate a planar shape extending along a width direction, a thickness direction, and a length direction, wherein the width direction corresponds to the first direction, the thickness direction corresponds to the second direction, and the length direction corresponds to the third direction.
    Type: Application
    Filed: June 24, 2026
    Publication date: October 15, 2026
    Inventors: Chih-Chien Pan, Li-Hui Cheng, Pu Wang
  • Patent number: 12761064
    Abstract: Disclosed are a liquid level switch system and a liquid level measurement method. The liquid level switch system has a transmitting probe, a receiving probe and a main unit. The transmitting probe is located at a warning position on the outer wall of a tank body, the receiving probe is located on the outer wall of the tank body, and the transmitting probe and the receiving probe are respectively connected to the main unit by means of cables. A piezoelectric plate is placed on an inclined block to change the incident angle of an ultrasonic signal entering the tank wall so as to generate a longitudinal wave signal and a transverse wave signal, and the main unit judges, according to a signal strength difference value between a longitudinal wave receiving signal and a transverse wave receiving signal, whether the liquid level of the tank body reaches the warning position.
    Type: Grant
    Filed: August 8, 2024
    Date of Patent: October 13, 2026
    Assignee: XI'AN DINGHUA ELECTRONICS CO., LTD
    Inventors: Pu Wang, Dinghua Wang, Rui Wang
  • Patent number: 12762294
    Abstract: The present disclosure discloses a determining method, a system, a reflector, a vertical tank external measurement liquid level meter and a mounting method thereof. An ultrasonic transmitting probe thereof is mounted on an outer wall of the measured vertical tank, and an ultrasonic signal emitted by the ultrasonic transmitting probe penetrates through a side wall of the vertical tank and generates an ultrasonic emission source at an inner wall of the vertical tank; an ultrasonic signal emitted by the ultrasonic emission source is emitted to the reflector, is returned to the position of the ultrasonic emission source according to the original path after passing through the liquid level of the measured vertical tank, penetrates through the side wall of the vertical tank and is received by a measuring head of the vertical tank external measurement liquid level meter mounted outside the side wall of the vertical tank.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: October 13, 2026
    Assignee: XI'AN DINGHUA ELECTRONICS CO., LTD.
    Inventors: Dinghua Wang, Rui Wang, Pu Wang
  • Publication number: 20260314397
    Abstract: An integrated circuit (IC) device includes a substrate, such as a printed circuit board (PCB) substrate. A chip assembly is disposed over the substrate. The chip assembly includes an IC, a plurality of electronic memory devices coupled to the IC, and a molding compound material that circumferentially surrounds the IC and the electronic memory devices collectively in a top view. A thermal interface material (TIM) is disposed over the chip assembly. The TIM includes an indium alloy, a gallium alloy, or an alloy that contains bismuth, indium, and tin. An adhesive dam is disposed over the substrate. The adhesive dam surrounds the chip assembly and the TIM laterally. A lid structure is disposed over the substrate and encapsulates the chip assembly therein. The lid structure includes one or more openings that expose portions of the TIM. The one or more openings accommodate an expansion of the TIM.
    Type: Application
    Filed: June 11, 2026
    Publication date: October 8, 2026
    Inventors: Ping-Yin Hsieh, Li-Hui Cheng, Pu Wang, Ying-Ching Shih
  • Publication number: 20260314398
    Abstract: A semiconductor device includes a package substrate, a package component, a heat dissipation component and a plurality of first adhesive patterns. The package component is bonded to the package substrate. The first adhesive patterns are adhered to and disposed between the package substrate and the heat dissipation component, the first adhesive patterns are disposed at a first side of the package component, and at least two of the first adhesive patterns are physically separated from each other and substantially aligned with each other in a first direction along which the first side is extended.
    Type: Application
    Filed: June 16, 2026
    Publication date: October 8, 2026
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20260305332
    Abstract: A method includes placing a package, which includes a first package component, a second package component, and an encapsulant encapsulating the first package component and the second package component therein. The method further includes attaching a first thermal interface material over the first package component, attaching a second thermal interface material different from the first thermal interface material over the second package component, an and attaching heat sink over both of the first thermal interface material and the second thermal interface material.
    Type: Application
    Filed: June 10, 2026
    Publication date: October 1, 2026
    Inventors: Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20260293669
    Abstract: A package structure includes a first package component including a semiconductor die and a thermal interface material (TIM) structure disposed on a first side of the first package component. The TIM structure includes a dielectric dam, a thermally conductive member surrounded by the dielectric dam and overlapping the semiconductor die, and a conductive layer interposed between the semiconductor die and the thermally conductive member.
    Type: Application
    Filed: May 17, 2026
    Publication date: September 24, 2026
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Hsieh, Li-Hui Cheng, Pu Wang, Szu-Wei Lu
  • Publication number: 20260293677
    Abstract: In an embodiment, a device includes a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a front-side of the package component. The device also includes a back-side metal layer on a back-side of the package component. The device also includes an indium thermal interface material on a back-side of the back-side metal layer. The device also includes a lid on a back-side of the indium thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.
    Type: Application
    Filed: June 2, 2026
    Publication date: September 24, 2026
    Inventors: Ping-Yin Hsieh, Chih-Hao Chen, Yi-Huan Liao, Pu Wang, Li-Hui Cheng
  • Publication number: 20260269895
    Abstract: A system for integrated millimeter-wave (mmWave) communication and sensing is disclosed. The system includes an antenna array configured to transmit and receive directional signals via multiple available RF chains, a memory storing a predefined codebook of beamforming patterns, and a processor executing instructions to optimize beamforming for both communication and sensing. During beam training intervals, the system transmits and receives beamforming patterns from the codebook, computing beamforming qualities for devices in communication. The system then selects multiple beamforming patterns that meet a communication criterion, such as a minimum data transmission threshold. The system further determines weights for a linear combination of the selected beamforming patterns to optimize sensing performance while maintaining communication reliability. The antenna array is configured to use the optimized beamforming pattern, ensuring efficient integrated operation within power and hardware constraints.
    Type: Application
    Filed: March 4, 2025
    Publication date: September 10, 2026
    Inventors: Pu Wang, Kareem Attiah, Hassan Mansour, Toshiaki Koike-Akino, Petros Boufounos
  • Publication number: 20260261998
    Abstract: A method for performing group-based association in a wireless communication network compliant with the IEEE 802.15.4 standard is provided. The method comprises receiving, by a network coordinator, association requests from a plurality of devices seeking to join the network. The method further comprises grouping the plurality of devices into one or more groups based on at least one grouping criterion selected from: (1) an association type indicating the priority of devices seeking association, (2) a time interval during which the association requests were received, (3) spatial proximity of the devices to the network coordinator, (4) a communication channel used by the devices, or (5) a beamforming direction relative to the network coordinator. The method further comprises transmitting, by the network coordinator, a group association response to each group, the association response including parameters required for devices within the group to complete the association process.
    Type: Application
    Filed: March 2, 2025
    Publication date: September 3, 2026
    Applicant: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Jianlin Guo, Pu Wang, Kieran Parsons, Petros Boufounos, Philip Orlik
  • Publication number: 20260256021
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a package unit and passive components disposed on and electrically connected to a circuit substrate, a dam disposed on the circuit substrate and enclosing the package unit and the passive components, and an underfill disposed between the package unit and the circuit substrate. The passive components are laterally spaced apart from the package unit, and sandwiched between the dam and the package unit. The underfill extends from the package unit to the passive components, and extends from the passive components to the dam. An outer periphery of the underfill is in contact with the dam.
    Type: Application
    Filed: February 25, 2025
    Publication date: August 27, 2026
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Yu Chen, Pu Wang, Li-Hui Cheng
  • Publication number: 20260246984
    Abstract: The present disclosure relates to the technical field of data processing, and discloses a video recommendation method and apparatus, an electronic device, a storage medium and a program product. The method includes: determining, in response to a first condition input on a first page, a historical live streaming video satisfying the first condition; displaying, in a display area of a second page, a display unit of at least one video segment in the historical live streaming video; displaying, in the display area of the first page, a first video segment in response to a selection instruction for the first video segment; and pushing the first video segment in response to an interaction operation on a push control in the first page.
    Type: Application
    Filed: February 11, 2026
    Publication date: August 20, 2026
    Inventors: Wei ZHOU, Zesheng WANG, Buyu LONG, Dan YE, Xiaodan HANG, Wei WU, Pu WANG, Haiwen WU, Kangyu TU, Jing LIANG
  • Publication number: 20260247961
    Abstract: A package structure and a method for forming a package structure are provided. The method includes disposing an upper chip-containing structure over a lower chip-containing structure and forming a protective layer laterally surrounding the upper chip-containing structure. The method also includes partially removing the protective layer to form an opening extending towards the lower chip-containing structure. The method further includes forming a thermal conductive structure at least partially filling the opening.
    Type: Application
    Filed: February 18, 2025
    Publication date: August 20, 2026
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yun WANG, Pu WANG, Chao-Wen SHIH, Kuo-Chiang TING, Yen-Ming CHEN
  • Patent number: 12713909
    Abstract: A method includes placing a package, which includes a first package component, a second package component, and an encapsulant encapsulating the first package component and the second package component therein. The method further includes attaching a first thermal interface material over the first package component, attaching a second thermal interface material different from the first thermal interface material over the second package component, and attaching a heat sink over both of the first thermal interface material and the second thermal interface material.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: August 18, 2026
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 12708270
    Abstract: The present disclosure provides a multi-modal imaging device based on Raman spectroscopy and optical coherence tomography. The multi-modal imaging device based on Raman spectroscopy and optical coherence tomography includes: a Raman spectroscopic analysis module configured to obtain Raman spectroscopic information of a target object on a first sampling position by using excitation light; an optical coherence tomography module configured to obtain at least one two-dimensional tissue structure image of the target object on a second sampling position by using imaging detection light; and a co-localization module configured to control the first sampling position of the excitation light in the Raman spectroscopic analysis module and/or the second sampling position in the optical coherence tomography module according to a determined concerned area of the target object, so that the first sampling position and the second sampling position are spatially co-localized in the concerned area.
    Type: Grant
    Filed: May 22, 2024
    Date of Patent: August 18, 2026
    Assignees: BEIHANG UNIVERSITY, SUZHOU SURGI-MASTER HIGH TECH CO., LTD.
    Inventors: Shuhua Yue, Shijie Zhu, Xun Chen, Pu Wang
  • Publication number: 20260239958
    Abstract: A packaging structure may be formed by: providing a composite package including at least one semiconductor die and a die frame; attaching the composite package to a packaging substrate to form a bonded assembly; providing a lid structure including a bottom plate portion, a top plate portion, a sidewall frame portion laterally surrounding a cavity located between the bottom plate portion and the top plate portion, and solid block portions vertically extending between the bottom plate portion and the top plate portion; and attaching the lid structure to the bonded assembly such that a thermal interface material (TIM) layer is interposed between the at least one semiconductor die and the bottom plate portion. The solid block portions do not have any areal overlap with the at least one semiconductor die in a plan view along a vertical direction.
    Type: Application
    Filed: February 10, 2025
    Publication date: August 13, 2026
    Inventors: Yi-Hsuan WU, Wei-Kong SHENG, Lipu Kris CHUANG, Pu WANG, Wensen HUNG, Yen-Ming CHEN
  • Patent number: 12707966
    Abstract: A semiconductor device includes a package substrate, a package component and at least one adhesive pattern. The package component has a thermal interface material (TIM) layer thereon. The adhesive pattern has a first surface facing the package substrate and a second surface opposite to the first surface, and the second surface of the at least one adhesive pattern is substantially coplanar with a surface of the TIM layer.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: August 11, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20260190926
    Abstract: A device structure may be manufactured by: disposing a semiconductor package on a package tray, wherein the package tray includes a tray base portion which laterally extends underneath the semiconductor package, a tray mesa portion which protrudes upward from the tray base portion and including a contiguous set of mesa-portion sidewalls, and a frame-shaped support portion including a continuous set of support-portion outer sidewalls that is laterally offset inward from a package area that is defined by a set of all sidewalls of the semiconductor package in a plan view; and anisotropically depositing an electromagnetic interference (EMI) shielding film on the set of all sidewalls of the semiconductor package and on a top surface of the semiconductor package.
    Type: Application
    Filed: December 29, 2024
    Publication date: July 2, 2026
    Inventors: Chih-Chien Pan, Li-Hui Cheng, Pu Wang
  • Patent number: 12672543
    Abstract: In an embodiment, a device includes a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a front-side of the package component. The device also includes a back-side metal layer on a back-side of the package component. The device also includes an indium thermal interface material on a back-side of the back-side metal layer. The device also includes a lid on a back-side of the indium thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: June 30, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Yin Hsieh, Chih-Hao Chen, Yi-Huan Liao, Pu Wang, Li-Hui Cheng