Patents by Inventor Pu Yu
Pu Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250127996Abstract: An injection needle device with safe-protection function includes: an injection module having an injection cylinder and a pullable piston rod; a needle module including a needle seat and an injection needle; the needle seat having a seat body and a buckle. In installation state, a safety sleeve covering movably around the injection cylinder between an installation position and a protection position. In the installing position, a first end portion of the safety sleeve is near the buckle and the second end portion thereof is near the handhold portion; while in the protection position, the first end portion is protruded from the injection cylinder for covering the injection needle and the second end portion is near the head portion of the injection cylinder. An inner side of the sleeve body is formed with a first and a second annular flange; and an annular groove is formed therebetween for confining the buckle.Type: ApplicationFiled: October 19, 2023Publication date: April 24, 2025Inventors: SHAN-PU YU, HUO-HSI SU
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Publication number: 20240408320Abstract: An injection needle apparatus with safe-protection function includes: an injection module having an injection cylinder and a pullable piston rod; a needle module including a needle seat and an injection needle; the needle seat having a seat body and a buckle. In installation state, a safety sleeve covering movably around the injection cylinder between an installation position and a protection position. In the installing position, a first end portion of the safety sleeve is near the buckle and the second end portion thereof is near the handhold portion; while in the protection position, the first end portion is protruded from the injection cylinder for covering the injection needle and the second end portion is near the head portion of the injection cylinder. An inner side of the sleeve body is formed with a first and a second annular flange; and an annular groove is formed therebetween for confining the buckle.Type: ApplicationFiled: June 6, 2023Publication date: December 12, 2024Inventors: SHAN-PU YU, Huo-Hsi Su
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Patent number: 11502253Abstract: A phase transformation electronic device comprises: a first conductive layer; a second conductive layer opposite to and spaced from the first conductive layer; a phase transformation material layer disposed between the first conductive layer and the second conductive layer, wherein the phase transformation material layer is formed by a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; and an ionic liquid layer disposed between the phase transformation material layer and the first conductive layer, wherein the ionic liquid layer is capable of providing hydrogen ions and oxygen ions.Type: GrantFiled: May 22, 2019Date of Patent: November 15, 2022Assignee: TSINGHUA UNIVERSITYInventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
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Patent number: 11434148Abstract: A hydrogen-containing transition metal oxide is provided. The hydrogen-containing transition metal oxide has a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5. The present disclosure further provides a primary battery by using the hydrogen-containing transition metal oxide as electrodes and a method for making the hydrogen-containing transition metal oxide.Type: GrantFiled: May 22, 2019Date of Patent: September 6, 2022Assignee: TSINGHUA UNIVERSITYInventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
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Patent number: 11217809Abstract: A solid-state fuel battery comprises an anode, a cathode spaced from the anode, and a solid-state electrolyte disposed between the anode and the cathode. A material of the solid-state electrolyte is a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5. A method for making the solid-state electrolyte for the solid-state fuel battery is further provided in the present disclosure.Type: GrantFiled: May 22, 2019Date of Patent: January 4, 2022Assignee: TSINGHUA UNIVERSITYInventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
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Patent number: 11018294Abstract: A method for regulating a phase transformation of a hydrogen-containing transition metal oxide comprises steps of: providing a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein the hydrogen-containing transition metal oxide is in form of a first phase, A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; soaking the hydrogen-containing transition metal oxide with a first ionic liquid capable of providing hydrogen ions and oxygen ions; and applying a gating voltage to the hydrogen-containing transition metal oxide with the first ionic liquid as a gate to regulate the phase transformation of the hydrogen-containing transition metal oxide.Type: GrantFiled: May 22, 2019Date of Patent: May 25, 2021Assignee: TSINGHUA UNIVERSITYInventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
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Publication number: 20200031685Abstract: A hydrogen-containing transition metal oxide is provided. The hydrogen-containing transition metal oxide has a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5. The present disclosure further provides a primary battery by using the hydrogen-containing transition metal oxide as electrodes and a method for making the hydrogen-containing transition metal oxide.Type: ApplicationFiled: May 22, 2019Publication date: January 30, 2020Applicant: Tsinghua UniversityInventors: PU YU, NIAN-PENG LU, JIAN WU, SHU-YUN ZHOU
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Publication number: 20190280202Abstract: A phase transformation electronic device comprises: a first conductive layer; a second conductive layer opposite to and spaced from the first conductive layer; a phase transformation material layer disposed between the first conductive layer and the second conductive layer, wherein the phase transformation material layer is formed by a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; and an ionic liquid layer disposed between the phase transformation material layer and the first conductive layer, wherein the ionic liquid layer is capable of providing hydrogen ions and oxygen ions.Type: ApplicationFiled: May 22, 2019Publication date: September 12, 2019Applicant: Tsinghua UniversityInventors: PU YU, NIAN-PENG LU, JIAN WU, SHU-YUN ZHOU
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Publication number: 20190280201Abstract: A method for regulating a phase transformation of a hydrogen-containing transition metal oxide comprises steps of: providing a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein the hydrogen-containing transition metal oxide is in form of a first phase, A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; soaking the hydrogen-containing transition metal oxide with a first ionic liquid capable of providing hydrogen ions and oxygen ions; and applying a gating voltage to the hydrogen-containing transition metal oxide with the first ionic liquid as a gate to regulate the phase transformation of the hydrogen-containing transition metal oxide.Type: ApplicationFiled: May 22, 2019Publication date: September 12, 2019Applicant: Tsinghua UniversityInventors: PU YU, NIAN-PENG LU, JIAN WU, SHU-YUN ZHOU
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Publication number: 20190280322Abstract: A solid-state fuel battery comprises an anode, a cathode spaced from the anode, and a solid-state electrolyte disposed between the anode and the cathode. A material of the solid-state electrolyte is a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5. A method for making the solid-state electrolyte for the solid-state fuel battery is further provided in the present disclosure.Type: ApplicationFiled: May 22, 2019Publication date: September 12, 2019Applicant: Tsinghua UniversityInventors: PU YU, NIAN-PENG LU, JIAN WU, SHU-YUN ZHOU
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Patent number: 9601474Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: June 15, 2015Date of Patent: March 21, 2017Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20150364457Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: June 15, 2015Publication date: December 17, 2015Applicant: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Patent number: 9059181Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: November 18, 2013Date of Patent: June 16, 2015Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20140217587Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: November 18, 2013Publication date: August 7, 2014Applicant: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Patent number: 8587091Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: June 26, 2012Date of Patent: November 19, 2013Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20130075941Abstract: A method for bonding a plastic member onto a metal housing is provided. A metal housing having an inner surface and an outer surface is prepared. A hollow-carved area is provided on the metal housing. The inner surface of the metal housing is subjected to physical process, thereby forming a bonding area. An adhesive layer is formed on the bonding area. A plastic mold member is formed on the adhesive layer by performing a first plastic injection molding. An optical plastic member is molded on the hollow-carved area by performing a second plastic injection molding.Type: ApplicationFiled: April 16, 2012Publication date: March 28, 2013Inventors: Yu-Chih Chang, Shih-Pu Yu, Chang-Li Liu
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Publication number: 20130075026Abstract: A method for bonding a plastic member onto a metal housing is provided. A metal housing having an inner surface and an outer surface is prepared. The inner surface of the metal housing is subjected to physical processing to thereby form a bonding area. An adhesive layer is formed on the bonding area. A plastic mold member is formed on the adhesive layer by plastic injection molding.Type: ApplicationFiled: April 15, 2012Publication date: March 28, 2013Inventors: Yu-Chih Chang, Shih-Pu Yu, Chang-Li Liu
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Patent number: 8314482Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: October 5, 2007Date of Patent: November 20, 2012Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Patent number: 8297088Abstract: An enclosure includes a main body, a cover for covering the main body, a movable member movably attached to an inner surface of the main body, and a latch member. The main body defines a through hole. The cover defines a through hole aligning with the through hole of the main body. The movable member defines a locking hole. The locking hole includes a small part and a large part communicating with the small part. The movable member is moved to align the large part of the locking hole with the through hole of the second sidewall. The latch member extends through the through hole of the cover, the through hole of the second sidewall, and the large part of the locking hole. The movable member then is restored, thereby the latch portion engaging in the small part of the locking hole.Type: GrantFiled: May 15, 2011Date of Patent: October 30, 2012Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Guang-Yi Zhang, Jia-Qi Fu, Pu-Yu Yao
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Publication number: 20120267765Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: June 26, 2012Publication date: October 25, 2012Applicant: Industrial Technology Research InstituteInventors: Shou-Lung CHEN, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu