Patents by Inventor Pu Yu
Pu Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240141553Abstract: A manufacturing process is described to evaluate and select raw semiconductor wafers in preparation for epitaxial layer formation. The manufacturing process first produces a single crystal ingot during which a seed pulling velocity and temperature gradient are closely controlled. The resulting ingot is vacancy-rich with relatively few self-interstitial defects. Selected wafers can advance to a high-temperature nitridation annealing operation that further reduces the number of interstitials while increasing the vacancies. Substrates characterized by a high vacancy density can then be used to optimize an epitaxial layer deposition process.Type: ApplicationFiled: March 28, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pu-Fang CHEN, Ching Yu Chen
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Publication number: 20240138059Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.Type: ApplicationFiled: November 23, 2022Publication date: April 25, 2024Applicant: Unimicron Technology Corp.Inventors: Kai-Ming Yang, Chia-Yu Peng, Cheng-Ta Ko, Pu-Ju Lin
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Publication number: 20240138063Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.Type: ApplicationFiled: November 15, 2022Publication date: April 25, 2024Applicant: Unimicron Technology Corp.Inventors: Ping-Tsung Lin, Kai-Ming Yang, Chia-Yu Peng, Pu-Ju Lin, Cheng-Ta Ko
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Publication number: 20240119130Abstract: A front-end device is configured to capture a light point image of an authenticatee and send the light point image to the back-end device, where the light point image is an image captured from the authenticatee under irradiation of multi-light points, and the light point image includes a face of the authenticatee. The back-end device of the authentication system is configured to perform face anti-spoofing detection on the authenticatee based on the received light point image to obtain an authentication result.Type: ApplicationFiled: June 22, 2023Publication date: April 11, 2024Inventors: Ziwen HU, Anping LI, Xiaoyuan YU, Pu CHEN
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Patent number: 11943877Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.Type: GrantFiled: March 2, 2022Date of Patent: March 26, 2024Assignee: Unimicron Technology Corp.Inventors: Wen-Yu Lin, Kai-Ming Yang, Chen-Hao Lin, Pu-Ju Lin, Cheng-Ta Ko, Chin-Sheng Wang, Guang-Hwa Ma, Tzyy-Jang Tseng
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Publication number: 20240077670Abstract: A semiconductor structure includes an optical interposer having at least one first photonic device in a first dielectric layer and at least one second photonic device in a second dielectric layer, wherein the second dielectric layer is disposed above the first dielectric layer. The semiconductor structure further includes a first die disposed on the optical interposer and electrically connected to the optical interposer; a first substrate under the optical interposer; and conductive connectors under the first substrate.Type: ApplicationFiled: January 13, 2023Publication date: March 7, 2024Inventors: Chih-Wei Tseng, Hsing-Kuo Hsia, Stefan Rusu, Chen-Hua Yu, Chewn-Pu Jou
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Patent number: 11502253Abstract: A phase transformation electronic device comprises: a first conductive layer; a second conductive layer opposite to and spaced from the first conductive layer; a phase transformation material layer disposed between the first conductive layer and the second conductive layer, wherein the phase transformation material layer is formed by a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; and an ionic liquid layer disposed between the phase transformation material layer and the first conductive layer, wherein the ionic liquid layer is capable of providing hydrogen ions and oxygen ions.Type: GrantFiled: May 22, 2019Date of Patent: November 15, 2022Assignee: TSINGHUA UNIVERSITYInventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
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Patent number: 11434148Abstract: A hydrogen-containing transition metal oxide is provided. The hydrogen-containing transition metal oxide has a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5. The present disclosure further provides a primary battery by using the hydrogen-containing transition metal oxide as electrodes and a method for making the hydrogen-containing transition metal oxide.Type: GrantFiled: May 22, 2019Date of Patent: September 6, 2022Assignee: TSINGHUA UNIVERSITYInventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
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Patent number: 11217809Abstract: A solid-state fuel battery comprises an anode, a cathode spaced from the anode, and a solid-state electrolyte disposed between the anode and the cathode. A material of the solid-state electrolyte is a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5. A method for making the solid-state electrolyte for the solid-state fuel battery is further provided in the present disclosure.Type: GrantFiled: May 22, 2019Date of Patent: January 4, 2022Assignee: TSINGHUA UNIVERSITYInventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
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Patent number: 11018294Abstract: A method for regulating a phase transformation of a hydrogen-containing transition metal oxide comprises steps of: providing a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein the hydrogen-containing transition metal oxide is in form of a first phase, A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; soaking the hydrogen-containing transition metal oxide with a first ionic liquid capable of providing hydrogen ions and oxygen ions; and applying a gating voltage to the hydrogen-containing transition metal oxide with the first ionic liquid as a gate to regulate the phase transformation of the hydrogen-containing transition metal oxide.Type: GrantFiled: May 22, 2019Date of Patent: May 25, 2021Assignee: TSINGHUA UNIVERSITYInventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
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Publication number: 20200031685Abstract: A hydrogen-containing transition metal oxide is provided. The hydrogen-containing transition metal oxide has a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5. The present disclosure further provides a primary battery by using the hydrogen-containing transition metal oxide as electrodes and a method for making the hydrogen-containing transition metal oxide.Type: ApplicationFiled: May 22, 2019Publication date: January 30, 2020Applicant: Tsinghua UniversityInventors: PU YU, NIAN-PENG LU, JIAN WU, SHU-YUN ZHOU
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Publication number: 20190280322Abstract: A solid-state fuel battery comprises an anode, a cathode spaced from the anode, and a solid-state electrolyte disposed between the anode and the cathode. A material of the solid-state electrolyte is a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5. A method for making the solid-state electrolyte for the solid-state fuel battery is further provided in the present disclosure.Type: ApplicationFiled: May 22, 2019Publication date: September 12, 2019Applicant: Tsinghua UniversityInventors: PU YU, NIAN-PENG LU, JIAN WU, SHU-YUN ZHOU
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Publication number: 20190280202Abstract: A phase transformation electronic device comprises: a first conductive layer; a second conductive layer opposite to and spaced from the first conductive layer; a phase transformation material layer disposed between the first conductive layer and the second conductive layer, wherein the phase transformation material layer is formed by a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; and an ionic liquid layer disposed between the phase transformation material layer and the first conductive layer, wherein the ionic liquid layer is capable of providing hydrogen ions and oxygen ions.Type: ApplicationFiled: May 22, 2019Publication date: September 12, 2019Applicant: Tsinghua UniversityInventors: PU YU, NIAN-PENG LU, JIAN WU, SHU-YUN ZHOU
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Publication number: 20190280201Abstract: A method for regulating a phase transformation of a hydrogen-containing transition metal oxide comprises steps of: providing a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein the hydrogen-containing transition metal oxide is in form of a first phase, A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; soaking the hydrogen-containing transition metal oxide with a first ionic liquid capable of providing hydrogen ions and oxygen ions; and applying a gating voltage to the hydrogen-containing transition metal oxide with the first ionic liquid as a gate to regulate the phase transformation of the hydrogen-containing transition metal oxide.Type: ApplicationFiled: May 22, 2019Publication date: September 12, 2019Applicant: Tsinghua UniversityInventors: PU YU, NIAN-PENG LU, JIAN WU, SHU-YUN ZHOU
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Patent number: 9601474Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: June 15, 2015Date of Patent: March 21, 2017Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20150364457Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: June 15, 2015Publication date: December 17, 2015Applicant: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Patent number: 9059181Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: November 18, 2013Date of Patent: June 16, 2015Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20140217587Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: ApplicationFiled: November 18, 2013Publication date: August 7, 2014Applicant: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Patent number: 8587091Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.Type: GrantFiled: June 26, 2012Date of Patent: November 19, 2013Assignee: Invensas CorporationInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
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Publication number: 20130075941Abstract: A method for bonding a plastic member onto a metal housing is provided. A metal housing having an inner surface and an outer surface is prepared. A hollow-carved area is provided on the metal housing. The inner surface of the metal housing is subjected to physical process, thereby forming a bonding area. An adhesive layer is formed on the bonding area. A plastic mold member is formed on the adhesive layer by performing a first plastic injection molding. An optical plastic member is molded on the hollow-carved area by performing a second plastic injection molding.Type: ApplicationFiled: April 16, 2012Publication date: March 28, 2013Inventors: Yu-Chih Chang, Shih-Pu Yu, Chang-Li Liu