Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.

Abstract: An image sensor module includes a first substrate, a second substrate provided over the first substrate, an image sensor device for receiving an image signal flip-chip bonded to the second substrate, and a semiconductor device for processing the image signal from the image sensor device embedded in the first substrate.

Abstract: Corrosion resistance of metallic components such as stainless steel components of vehicles, and especially aluminum-based components of aircraft, is enhanced by application of an e-coat paint or primer which is enhanced by incorporation of cerium ions into the e-coat electrolytic bath. The resulting overall coating includes a cerium-based layer under a cerium-enhanced e-coat paint or primer layer.

Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Abstract: A method and a device for enhancing the solderability of a lead-free component are provided. The provided method is compatible with the conventional soldering process and is capable of improving the wetting ability of the solder so as to enhance the solderability and the ability of anti-oxidation thereof. Besides, it is also achievable for providing a recognizable lead-free device so as to prevent the process confusion.

Abstract: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.

Abstract: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.

Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.

Abstract: An image sensor module includes a first substrate, a second substrate provided over the first substrate, an image sensor device for receiving an image signal flip-chip bonded to the second substrate, and a semiconductor device for processing the image signal from the image sensor device embedded in the first substrate.

Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: A new and improved image sensor packaging structure and method. The image sensor packaging structure includes a glass substrate. A bond pad film, on which is provided multiple, interior flip-chip bond pads and exterior BGA (ball grid array) bond pads, is provided on the glass substrate. An inverted image sensor chip is bonded to the flip-chip bond pads on the glass substrate. The light-receiving face of the chip faces the glass substrate typically through a window provided in the bond pad film. Solder bumps are provided on the BGA bond pads on the bond pad film, and bond pads on a PCB (printed circuit board) are bonded to the respective solder bumps.

Abstract: Primer coating compositions containing rare earth compounds having good adhesion to metals, including aluminum and aluminum alloys, are provided herewith. Also disclosed are processes for preparing said coating compositions, methods of using same, as well as substrates coated with the coating compositions.

Abstract: A coating composition comprising an effective corrosion-inhibiting amount of a rare earth compound, a neutral to slightly acidic generating extender or an acidic generating extender, or combinations thereof is provided. In one embodiment, the corrosion-inhibiting components are combined with other components such as extenders, amino acids and amino acid derivatives, gelatin and gelatin derivatives, organic-based exchange resins, and combinations thereof, to enhance the corrosion resistance of the resultant coating film. The coating compositions have good adhesion to substrates such as metals, including aluminum and aluminum alloys.

Abstract: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.

Abstract: A coating composition comprising an effective corrosion-inhibiting amount of a carbon pigment is provided. In one embodiment, the corrosion-inhibiting carbon pigment is further comprising other components such as extenders, including neutral to slightly acidic generating extenders and acidic generating extenders, are earth compounds, amino acids and amino acid derivatives, gelatin and gelatin derivatives, organic-based exchange resins, and combinations thereof, to enhance the corrosion resistance of the resultant coating film. In one embodiment, the carbon pigment is a surface-modified carbon pigment. The coating compositions have good adhesion to substrates such as metals, including aluminum and aluminum alloys.

Abstract: Corrosion resistance of metallic components such as stainless steel components of vehicles, and especially aluminum-based components of aircraft, is enhanced by application of an e-coat paint or primer which is enhanced by incorporation of cerium ions into the e-coat electrolytic bath. The resulting overall coating includes a cerium-based layer under a cerium-enhanced e-coat paint or primer layer.

Abstract: A process for enhancing the corrosion resistance of an aluminum-containing component with a cerium based coating. An aluminum-containing cathode and an oxygen-evolving anode are immersed in an electrolyte comprising water, solvent, oxidizing agent and cerium ions. An electrical current is passed through the electrolyte by applying electrical current to deposit a cerium based coating onto the cathode. An electrolyte for use in depositing a cerium based coating. An electrodeposited cerium-based coating. An aluminum aircraft structural component having a cerium-based coating thereon.