Patents by Inventor Pulkit Shah
Pulkit Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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HIGH-VOLTAGE TOLERANT, HIGH-SPEED REVERSE CURRENT DETECTION AND PROTECTION FOR BUCK-BOOST CONVERTERS
Publication number: 20240044951Abstract: A controller includes a buck gate driver coupled to first high-side switch and first low-side switch of a buck-boost (BB) converter. A zero crossing detection (ZCD) comparator is coupled to first low-side switch. The ZCD comparator is to, while the BB converter operates in buck mode: detect zero current flow through inductor; and turn off first low-side switch in response to detecting the zero current. A boost gate driver is coupled to second high-side switch and second low-side switch of the BB converter. A reverse current detection (RCD) comparator coupled to second high-side switch. The RCD comparator is to, while the BB converter operates in boost mode: detect zero current flow through second high-side switch; and turn off second high-side switch in response to detecting the zero current.Type: ApplicationFiled: October 18, 2023Publication date: February 8, 2024Applicant: Cypress Semiconductor CorporationInventors: Partha Mondal, Tudu Balia, Hariom Rai, Pulkit Shah -
Patent number: 11862959Abstract: A system includes a first USB Type-C Power Delivery (USB-C/PD) port and a control circuit operatively coupled to the first USB-C/PD port. The control circuit is configured to determine whether a short circuit condition has occurred based on a first threshold voltage. The control circuit is also configured to turn off a ground isolation switch when short circuit condition occurs. The control circuit is further configured to determine a whether a voltage on a ground line is less than a second threshold voltage. The control circuit is further configured to turn on the ground isolation switch when the voltage on the ground line is less than the second threshold voltage. The control circuit may perform one or more error recovery operations after turning on the ground isolation switch.Type: GrantFiled: April 26, 2022Date of Patent: January 2, 2024Assignee: Cypress Semiconductor CorporationInventors: Arun Khamesra, Hariom Rai, Pulkit Shah
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Patent number: 11848552Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: GrantFiled: May 6, 2022Date of Patent: December 19, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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High-voltage tolerant, high-speed reverse current detection and protection for buck-boost converters
Patent number: 11821927Abstract: A controller includes a buck gate driver coupled to first high-side switch and first low-side switch of a buck-boost (BB) converter. A zero crossing detection (ZCD) comparator is coupled to first low-side switch. The ZCD comparator is to, while the BB converter operates in buck mode: detect zero current flow through inductor; and turn off first low-side switch in response to detecting the zero current. A boost gate driver is coupled to second high-side switch and second low-side switch of the BB converter. A reverse current detection (RCD) comparator coupled to second high-side switch. The RCD comparator is to, while the BB converter operates in boost mode: detect zero current flow through second high-side switch; and turn off second high-side switch in response to detecting the zero current.Type: GrantFiled: August 6, 2021Date of Patent: November 21, 2023Assignee: Cypress Semiconductor CorporationInventors: Partha Mondal, Tudu Balia, Hariom Rai, Pulkit Shah -
Publication number: 20230344213Abstract: A system includes a first USB Type-C Power Delivery (USB-C/PD) port and a control circuit operatively coupled to the first USB-C/PD port. The control circuit is configured to determine whether a short circuit condition has occurred based on a first threshold voltage. The control circuit is also configured to turn off a ground isolation switch when short circuit condition occurs. The control circuit is further configured to determine a whether a voltage on a ground line is less than a second threshold voltage. The control circuit is further configured to turn on the ground isolation switch when the voltage on the ground line is less than the second threshold voltage. The control circuit may perform one or more error recovery operations after turning on the ground isolation switch.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Applicant: Cypress Semiconductor CorporationInventors: Arun Khamesra, Hariom RAI, Pulkit SHAH
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Publication number: 20230299676Abstract: Universal Serial Bus Type-C (USB-C) controllers with a floating gate driver with programmable drive strength for a wide range of USB power delivery applications in electronic devices described. A USB-C controller includes a floating gate driver and control logic. The floating gate driver includes p-channel field-effect transistors (FETs) coupled in parallel between a first terminal and a second terminal and p-channel pre-gate drivers. Each p-channel pre-gate driver is coupled to a gate of one of the p-channel FETs. The floating gate driver includes n-channel FETs coupled in parallel between the second terminal and a third terminal and n-channel pre-gate drivers, each n-channel pre-gate driver being coupled to a gate of one of the plurality of n-channel FETs. The control logic sends one or more control signals to activate a first number of p-channel pre-gate drivers and a second number of n-channel pre-gate drivers based on an output voltage.Type: ApplicationFiled: March 16, 2022Publication date: September 21, 2023Applicant: Cypress Semiconductor CorporationInventors: Hemant P. Vispute, Partha MONDAL, Tudu Rushika Banam BALIA, Arun KHAMESRA, Pulkit SHAH, Hariom RAI
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Publication number: 20230291314Abstract: A mode-transition architecture for USB controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes a controller coupled to a slope compensation circuit, the controller to detect a transition of a buck-boost converter from a first mode having a first duty cycle to a second mode having a second duty cycle that is less or more than the first duty cycle. The controller controls the slope compensation circuit to nullify an error in an output caused by the transition. The controller can cause the slope compensation circuit to apply a charge stored in a capacitor during a first cycle to start a second cycle with a higher voltage than the first cycle.Type: ApplicationFiled: May 1, 2023Publication date: September 14, 2023Applicant: Cypress Semiconductor CorporationInventors: Rajesh Karri, Arun Khamesra, Pulkit Shah, Hariom Rai
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Patent number: 11736023Abstract: Communicating fault conditions between primary-side and secondary-side controllers of a Universal Serial Bus Power Delivery (USB-PD) device is described. The primary-side controller receives a control signal from the secondary-side controller across a galvanic isolation barrier. The primary-side controller converts the control signal into a first pulse signal and applies the first pulse signal to control a primary-side switch. When the primary-side controller detects that a first fault condition has occurred, the primary-side controller communicates a first information signal about the first fault condition to the secondary-side controller across the galvanic isolation barrier. The first information signal is generated by converting the control signal into a second pulse signal having a different pulse width than the first pulse signal. The primary-side controller applies the second pulse signal to control the primary-side power switch.Type: GrantFiled: March 10, 2021Date of Patent: August 22, 2023Assignee: Cypress Semiconductor CorporationInventors: Arun Khamesra, Hariom Rai, Pulkit Shah
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Publication number: 20230223858Abstract: A secondary-side-controller for a QR flyback converter and method for operating the same are provided. Generally, the secondary-side-controller includes a driver configured to control a power-switch (PS) on a primary side of converter to turn on the PS when a sinusoidal input voltage to the converter is at one of a plurality of valleys, an analog-to-digital-converter (ADC) to read the input voltage, output voltage, and load current, and generate digital signals based thereon. A valley-controller coupled to the driver, ADC, a look-up-table and a pulse width modulator (PWM) receives the signals from the ADC and using the look-up-table determines at which valley of the plurality of valleys to couple a PWM signal from the PWM to the driver. The valley-controller is operable for each switching cycle of the PS to increment, decrement or leave unchanged the valley at which the PWM signal is coupled from the PWM to the driver.Type: ApplicationFiled: January 13, 2022Publication date: July 13, 2023Applicant: Cypress Semiconductor CorporationInventors: Pulkit SHAH, Arun KHAMESRA, Hariom RAI
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Patent number: 11671013Abstract: An IC controller for USB Type-C device includes an error amplifier (EA), which includes an EA output coupled to a PWM comparator of a buck-boost converter; a first transconductance amplifier to adjust a current at the EA output, the first transconductance amplifier operating in a constant voltage mode; and a second transconductance amplifier to adjust the current at the EA output, the second transconductance amplifier operating in a constant current mode. A first set of programmable registers is to store a first set of increasingly higher transconductance values. A second set of programmable registers is to store a second set of increasingly higher transconductance values. Control logic is to: cause the first transconductance amplifier to operate while sequentially using transconductance values stored in the first set of programmable registers; and cause the second transconductance amplifier to operate while sequentially using transconductance values stored in the second set of programmable registers.Type: GrantFiled: August 31, 2021Date of Patent: June 6, 2023Assignee: Cypress Semiconductor CorporationInventors: Arun Khamesra, Hariom Rai, Rajesh Karri, Pulkit Shah
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Patent number: 11658573Abstract: A mode-transition architecture for USB controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes a controller coupled to a slope compensation circuit, the controller to detect a transition of a buck-boost converter from a first mode having a first duty cycle to a second mode having a second duty cycle that is less or more than the first duty cycle. The controller controls the slope compensation circuit to nullify an error in an output caused by the transition. The controller can cause the slope compensation circuit to apply a charge stored in a capacitor during a first cycle to start a second cycle with a higher voltage than the first cycle.Type: GrantFiled: January 13, 2021Date of Patent: May 23, 2023Assignee: Cypress Semiconductor CorporationInventors: Rajesh Karri, Arun Khamesra, Pulkit Shah, Hariom Rai
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Patent number: 11658574Abstract: An IC controller for a USB Type-C device includes a register that is programmable to store a pulse width and a frequency. A buck-boost converter of the controller includes a first high-side switch and a second high-side switch. Control logic is coupled to the register and gates of the first/second high-side switches. To perform a soft start in one of buck mode or boost mode, the control logic: causes the second high-side switch to operate in diode mode; retrieves values of the pulse width and the frequency from the register; causes the first high-side switch to turn on using pulses having the pulse width and at the frequency; detects an output voltage at the output terminal of the buck-boost converter that exceeds a threshold value; and in response to the detection, transfers control of the buck-boost converter to an error amplifier loop coupled to the control logic.Type: GrantFiled: May 6, 2021Date of Patent: May 23, 2023Assignee: Cypress Semiconductor CorporationInventors: Hariom Rai, Pulkit Shah, Arun Khamesra, Rajesh Karri, Praveen Suresh
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Patent number: 11625355Abstract: A multi-port USB Type-C® Power Delivery (USB-C/PD) power converter for switching clock phase shifts is described herein. The multi-port USB-C/PD power converter includes a first PD port, a second PD port, and a power controller coupled to the first and second PD ports. The power controller includes a first phased clock generator to generate a first phase-shifted clock signal by shifting a clock signal by a first phase with respect to a reference clock signal, and a second phased clock generator to generate a second phase-shifted clock signal to generate a second phased-shifted clock signal by shifting the clock signal by a second phase with respect to the reference clock signal. The first PD port and the second PD port output power in response to a first control signal based on the first phase-shifted clock signal and a second control signal based on the second phase-shifted clock signal, respectively.Type: GrantFiled: August 24, 2021Date of Patent: April 11, 2023Assignee: Cypress Semiconductor CorporationInventors: Arun Khamesra, Pulkit Shah, Praveen Suresh, Hariom Rai
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Patent number: 11609622Abstract: A multi-port Universal Serial Bus Type-C (USB-C) controller with ground and supply cable compensation technologies is described. A USB-C controller includes a first power control circuit (PCU) coupled to a system ground terminal and a first ground terminal and a second PCU coupled to the system ground terminal and a second ground terminal. The first PCU receives a first ground signal indicative of a first ground potential at a first USB-C connector and adjusts a first power voltage line (VBUS) signal on the first VBUS terminal based on the first ground signal and the system ground. The second PCU receives a second ground signal indicative of a second ground potential at a second USB-C connector and adjusts a second VBUS signal on the second VBUS terminal based on the second ground signal and the system ground.Type: GrantFiled: May 12, 2021Date of Patent: March 21, 2023Assignee: Cypress Semiconductor CorporationInventors: Pulkit Shah, Hariom Rai
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Patent number: 11527957Abstract: A mode-transition architecture for USB Type-C controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes controller includes a controller coupled to a slope compensation circuit, the controller to cause the slope compensation circuit to apply a first slope compensation to the input current in a first mode in which the buck-boost converter is operating in a discontinuous conduction mode (DCM). The controller detects a transition of the buck-boost converter from a first mode having a first duty cycle to a second mode and causes the slope compensation circuit to apply a second slope compensation to the input current. The second slope compensation starts at a maximum offset of the first slope compensation.Type: GrantFiled: January 13, 2021Date of Patent: December 13, 2022Assignee: Cypress Semiconductor CorporationInventors: Rajesh Karri, Arun Khamesra, Pulkit Shah, Hariom Rai
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Patent number: 11522458Abstract: An apparatus includes a first high-side driver of a buck-boost converter, the first high-side driver powered between a first bootstrap voltage (VBST1) and a first output voltage of a first high-side switch driven by the first high-side driver. A second high-side driver is powered between a second bootstrap voltage (VBST2) and a second output voltage of a second high-side switch driven by the second high-side driver. A comparator is to detect VBST1 drop below a threshold value with respect to the first output voltage when the buck-boost converter is in boost mode. A leakage control circuit is to boost, using VBST2 as a voltage source, VBST1 each cycle of boost mode in which an output of the comparator is enabled.Type: GrantFiled: May 13, 2021Date of Patent: December 6, 2022Assignee: Cypress Semiconductor CorporationInventors: Hemant Prakash Vispute, Partha Mondal, Pulkit Shah, Hariom Rai
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Publication number: 20220263309Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: ApplicationFiled: May 6, 2022Publication date: August 18, 2022Inventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Patent number: 11355918Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: GrantFiled: October 23, 2020Date of Patent: June 7, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Patent number: 11316441Abstract: Controlling gate-source voltage with a gate driver in a secondary-side integrated circuit (IC) controller for a secondary-controlled AC-DC converter is described. In an example embodiment, the gate driver is configured to programmably control the gate-source voltage and the slew rate of a secondary-side provider field effect transistor (FET) in the converter.Type: GrantFiled: August 6, 2020Date of Patent: April 26, 2022Assignee: Cypress Semiconductor CorporationInventor: Pulkit Shah
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Publication number: 20220066980Abstract: A multi-port USB Power Delivery Type-C (USB-C/PD) power converter for switching clock phase shifts is described herein. The multi-port USB-C/PD power converter includes a first PD port, a second PD port, and a power controller coupled to the first and second PD ports. The power controller includes a first phased clock generator to generate a first phase-shifted clock signal by shifting a clock signal by a first phase with respect to a reference clock signal, and a second phased clock generator to generate a second phase-shifted clock signal to generate a second phased-shifted clock signal by shifting the clock signal by a second phase with respect to the reference clock signal. The first PD port and the second PD port output power in response to a first control signal based on the first phase-shifted clock signal and a second control signal based on the second phase-shifted clock signal, respectively.Type: ApplicationFiled: August 24, 2021Publication date: March 3, 2022Applicant: Cypress Semiconductor CorporationInventors: Arun Khamesra, Pulkit Shah, Praveen Suresh, Hariom Rai