Patents by Inventor Pulkit Shah

Pulkit Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220069708
    Abstract: A mode-transition architecture for USB controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes a controller coupled to a slope compensation circuit, the controller to detect a transition of a buck-boost converter from a first mode having a first duty cycle to a second mode having a second duty cycle that is less or more than the first duty cycle. The controller controls the slope compensation circuit to nullify an error in an output caused by the transition. The controller can cause the slope compensation circuit to apply a charge stored in a capacitor during a first cycle to start a second cycle with a higher voltage than the first cycle.
    Type: Application
    Filed: January 13, 2021
    Publication date: March 3, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Rajesh Karri, Arun Khamesra, Pulkit Shah, Hariom Rai
  • Publication number: 20220066532
    Abstract: A multi-port Universal Serial Bus Type-C (USB-C) controller with ground and supply cable compensation technologies is described. A USB-C controller includes a first power control circuit (PCU) coupled to a system ground terminal and a first ground terminal and a second PCU coupled to the system ground terminal and a second ground terminal. The first PCU receives a first ground signal indicative of a first ground potential at a first USB-C connector and adjusts a first power voltage line (VBUS) signal on the first VBUS terminal based on the first ground signal and the system ground. The second PCU receives a second ground signal indicative of a second ground potential at a second USB-C connector and adjusts a second VBUS signal on the second VBUS terminal based on the second ground signal and the system ground.
    Type: Application
    Filed: May 12, 2021
    Publication date: March 3, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Pulkit Shah, Hariom Rai
  • Publication number: 20220069710
    Abstract: An apparatus includes a first high-side driver of a buck-boost converter, the first high-side driver powered between a first bootstrap voltage (VBST1) and a first output voltage of a first high-side switch driven by the first high-side driver. A second high-side driver is powered between a second bootstrap voltage (VBST2) and a second output voltage of a second high-side switch driven by the second high-side driver. A comparator is to detect VBST1 drop below a threshold value with respect to the first output voltage when the buck-boost converter is in boost mode. A leakage control circuit is to boost, using VBST2 as a voltage source, VBST1 each cycle of boost mode in which an output of the comparator is enabled.
    Type: Application
    Filed: May 13, 2021
    Publication date: March 3, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Hemant Prakash Vispute, Partha Mondal, Pulkit Shah, Hariom Rai
  • Publication number: 20220069715
    Abstract: A mode-transition architecture for USB Type-C controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes controller includes a controller coupled to a slope compensation circuit, the controller to cause the slope compensation circuit to apply a first slope compensation to the input current in a first mode in which the buck-boost converter is operating in a discontinuous conduction mode (DCM). The controller detects a transition of the buck-boost converter from a first mode having a first duty cycle to a second mode and causes the slope compensation circuit to apply a second slope compensation to the input current. The second slope compensation starts at a maximum offset of the first slope compensation.
    Type: Application
    Filed: January 13, 2021
    Publication date: March 3, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Rajesh Karri, Arun Khamesra, Pulkit Shah, Hariom Rai
  • Publication number: 20220069709
    Abstract: An IC controller for a USB Type-C device includes a register that is programmable to store a pulse width and a frequency. A buck-boost converter of the controller includes a first high-side switch and a second high-side switch. Control logic is coupled to the register and gates of the first/second high-side switches. To perform a soft start in one of buck mode or boost mode, the control logic: causes the second high-side switch to operate in diode mode; retrieves values of the pulse width and the frequency from the register; causes the first high-side switch to turn on using pulses having the pulse width and at the frequency; detects an output voltage at the output terminal of the buck-boost converter that exceeds a threshold value; and in response to the detection, transfers control of the buck-boost converter to an error amplifier loop coupled to the control logic.
    Type: Application
    Filed: May 6, 2021
    Publication date: March 3, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Hariom Rai, Pulkit Shah, Arun Khamesra, Karri Rajesh, Praveen Suresh
  • Publication number: 20220069713
    Abstract: An IC controller for USB Type-C device includes an error amplifier (EA), which includes an EA output coupled to a PWM comparator of a buck-boost converter; a first transconductance amplifier to adjust a current at the EA output, the first transconductance amplifier operating in a constant voltage mode; and a second transconductance amplifier to adjust the current at the EA output, the second transconductance amplifier operating in a constant current mode. A first set of programmable registers is to store a first set of increasingly higher transconductance values. A second set of programmable registers is to store a second set of increasingly higher transconductance values. Control logic is to: cause the first transconductance amplifier to operate while sequentially using transconductance values stored in the first set of programmable registers; and cause the second transconductance amplifier to operate while sequentially using transconductance values stored in the second set of programmable registers.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 3, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Hariom Rai, Rajesh Karri, Pulkit Shah
  • Publication number: 20220069712
    Abstract: A controller includes a buck gate driver coupled to first high-side switch and first low-side switch of a buck-boost (BB) converter. A zero crossing detection (ZCD) comparator is coupled to first low-side switch. The ZCD comparator is to, while the BB converter operates in buck mode: detect zero current flow through inductor; and turn off first low-side switch in response to detecting the zero current. A boost gate driver is coupled to second high-side switch and second low-side switch of the BB converter. A reverse current detection (RCD) comparator coupled to second high-side switch. The RCD comparator is to, while the BB converter operates in boost mode: detect zero current flow through second high-side switch; and turn off second high-side switch in response to detecting the zero current.
    Type: Application
    Filed: August 6, 2021
    Publication date: March 3, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Partha Mondal, Tudu Balia, Hariom Rai, Pulkit Shah
  • Patent number: 11201556
    Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC controller of the AC-DC converter includes a peak-detector block coupled to detect peak voltages sensed on a SR-SNS pin. The peak-detector block comprises a peak comparator, a sample-and-hold (S/H) circuit, and a DC offset circuit. The peak comparator is coupled to receive a sinusoidal input from the SR-SNS pin. The S/H circuit is coupled to sample the sinusoidal input and to provide a peak sampled voltage. The DC offset voltage circuit is coupled between the output of the S/H circuit and a reference voltage input of the peak comparator to subtract a DC offset voltage from the peak sampled voltage.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: December 14, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Saravanan Murugesan, Karri Rajesh, Pulkit Shah, Arun Khamesra, Hariom Rai
  • Publication number: 20210344267
    Abstract: Communicating fault conditions between primary-side and secondary-side controllers of a Universal Serial Bus Power Delivery (USB-PD) device is described. The primary-side controller receives a control signal from the secondary-side controller across a galvanic isolation barrier. The primary-side controller converts the control signal into a first pulse signal and applies the first pulse signal to control a primary-side switch. When the primary-side controller detects that a first fault condition has occurred, the primary-side controller communicates a first information signal about the first fault condition to the secondary-side controller across the galvanic isolation barrier. The first information signal is generated by converting the control signal into a second pulse signal having a different pulse width than the first pulse signal. The primary-side controller applies the second pulse signal to control the primary-side power switch.
    Type: Application
    Filed: March 10, 2021
    Publication date: November 4, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Hariom Rai, Pulkit Shah
  • Patent number: 11139743
    Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC) controller of the AC-DC converter includes a SR-SNS pin, a VBUS_IN pin, a first voltage-to-current converter, a sample-and-hold (S/H) circuit, a second voltage-to-current converter, and a signal generation circuit. The first voltage-to-current converter is coupled to remove a component of the output bus voltage sensed on the VBUS_IN pin from the voltage sensed on the SR-SNS pin. The S/H circuit is coupled to sample the voltage sensed on the SR-SNS pin and to provide a sampled voltage. The second voltage-to-current converter is coupled to convert the sampled voltage to a feed-forward current. The signal generation circuit is coupled to receive the feed-forward current and to generate feed-forward signals used to control operation of a primary side of the AC-DC converter.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: October 5, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Partha Mondal, Hemant P. Vispute, Arun Khamesra, Hariom Rai, Pulkit Shah
  • Patent number: 10951107
    Abstract: Communicating fault indications between primary and secondary controller in a secondary-controlled flyback converter is described. In one embodiment, an apparatus includes a primary-side field effect transistor (FET) coupled to a flyback transformer coupled to the primary-side FET, and a primary-side controller coupled to the flyback transformer. The primary-side controller is configured to receive a signal from a secondary-side controller across a galvanic isolation barrier, apply a pulse signal to the primary-side FET in response to the signal to turn-on and turn-off the primary-side FET, communicate information to the secondary-side controller across the flyback transformer by varying a first pulse width of the pulse signal to a second pulse width and applying the pulse signal with the second pulse width to the primary-side FET.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 16, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Hariom Rai, Pulkit Shah
  • Publication number: 20210058005
    Abstract: Controlling gate-source voltage with a gate driver in a secondary-side integrated circuit (C) controller for a secondary-controlled AC-DC converter is described. In an example embodiment, the gate driver is configured to programmably control the gate-source voltage and the slew rate of a secondary-side provider field effect transistor (FET) in the converter.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 25, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventor: Pulkit Shah
  • Publication number: 20210044101
    Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
  • Patent number: 10910954
    Abstract: A secondary-side controller for an AC-DC converter that has a single synchronous rectifier sensing (SR_SNS) terminal, coupled to a synchronous rectifier (SR) of the AC-DC converter, and a voltage divider circuit coupled to the single SR_SNS terminal configured to provide signals to a sensing circuit. The voltage divider includes an active diode, an internal resistive element, and a switch, in which the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison result of a voltage at the single SR_SNS terminal and a reference voltage.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: February 2, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Pulkit Shah, Karri Rajesh, Arun Khamesra, Hariom Rai
  • Patent number: 10903752
    Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. In an example embodiment, an integrated circuit (IC) controller for the secondary side of the AC-DC converter comprises a zero-crossing detector (ZCD) block and a negative-sensing (NSN) block coupled to a terminal. The terminal is configured to receive an input signal from a drain node of a SR circuit on the secondary side of the AC-DC converter. The ZCD block is configured to determine when a voltage of the input signal reaches 0V. The NSN block is configured to determine a negative voltage of the input signal. An internal rectifier, coupled between the terminal and local ground, is configured to ensure that substantially no current flows through the terminal during operation of the ZCD block and the NSN block.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: January 26, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Hariom Rai, Pulkit Shah
  • Publication number: 20200412265
    Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC controller of the AC-DC converter includes a peak-detector block coupled to detect peak voltages sensed on a SR-SNS pin. The peak-detector block comprises a peak comparator, a sample-and-hold (S/H) circuit, and a DC offset circuit. The peak comparator is coupled to receive a sinusoidal input from the SR-SNS pin. The S/H circuit is coupled to sample the sinusoidal input and to provide a peak sampled voltage. The DC offset voltage circuit is coupled between the output of the S/H circuit and a reference voltage input of the peak comparator to subtract a DC offset voltage from the peak sampled voltage.
    Type: Application
    Filed: April 15, 2020
    Publication date: December 31, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Saravanan Murugesan, Karri Rajesh, Pulkit Shah, Arun Khamesra, Hariom Rai
  • Publication number: 20200412263
    Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. In an example embodiment, an integrated circuit (IC) controller for the secondary side of the AC-DC converter comprises a zero-crossing detector (ZCD) block and a negative-sensing (NSN) block coupled to a terminal. The terminal is configured to receive an input signal from a drain node of a SR circuit on the secondary side of the AC-DC converter. The ZCD block is configured to determine when a voltage of the input signal reaches 0V. The NSN block is configured to determine a negative voltage of the input signal. An internal rectifier, coupled between the terminal and local ground, is configured to ensure that substantially no current flows through the terminal during operation of the ZCD block and the NSN block.
    Type: Application
    Filed: January 10, 2020
    Publication date: December 31, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Hariom Rai, Pulkit Shah
  • Publication number: 20200412231
    Abstract: Communicating fault indications between primary and secondary controller in a secondary-controlled flyback converter is described. In one embodiment, an apparatus includes a primary-side field effect transistor (FET) coupled to a flyback transformer coupled to the primary-side FET, and a primary-side controller coupled to the flyback transformer. The primary-side controller is configured to receive a signal from a secondary-side controller across a galvanic isolation barrier, apply a pulse signal to the primary-side FET in response to the signal to turn-on and turn-off the primary-side FET, communicate information to the secondary-side controller across the flyback transformer by varying a first pulse width of the pulse signal to a second pulse width and applying the pulse signal with the second pulse width to the primary-side FET.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Hariom Rai, Pulkit Shah
  • Publication number: 20200412266
    Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC) controller of the AC-DC converter includes a SR-SNS pin, a VBUS_IN pin, a first voltage-to-current converter, a sample-and-hold (S/H) circuit, a second voltage-to-current converter, and a signal generation circuit. The first voltage-to-current converter is coupled to remove a component of the output bus voltage sensed on the VBUS_IN pin from the voltage sensed on the SR-SNS pin. The S/H circuit is coupled to sample the voltage sensed on the SR-SNS pin and to provide a sampled voltage. The second voltage-to-current converter is coupled to convert the sampled voltage to a feed-forward current. The signal generation circuit is coupled to receive the feed-forward current and to generate feed-forward signals used to control operation of a primary side of the AC-DC converter.
    Type: Application
    Filed: May 26, 2020
    Publication date: December 31, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Partha Mondal, Hemant P. Vispute, Arun Khamesra, Hariom Rai, Pulkit Shah
  • Patent number: 10855069
    Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: December 1, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes