Abstract: A secondary-side controller for an AC-DC converter that has a single synchronous rectifier sensing (SR_SNS) terminal, coupled to a synchronous rectifier (SR) of the AC-DC converter, and a voltage divider circuit coupled to the single SR_SNS terminal configured to provide signals to a sensing circuit. The voltage divider includes an active diode, an internal resistive element, and a switch, in which the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison result of a voltage at the single SR_SNS terminal and a reference voltage.

Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. In an example embodiment, an integrated circuit (IC) controller for the secondary side of the AC-DC converter comprises a zero-crossing detector (ZCD) block and a negative-sensing (NSN) block coupled to a terminal. The terminal is configured to receive an input signal from a drain node of a SR circuit on the secondary side of the AC-DC converter. The ZCD block is configured to determine when a voltage of the input signal reaches 0V. The NSN block is configured to determine a negative voltage of the input signal. An internal rectifier, coupled between the terminal and local ground, is configured to ensure that substantially no current flows through the terminal during operation of the ZCD block and the NSN block.

Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC) controller of the AC-DC converter includes a SR-SNS pin, a VBUS_IN pin, a first voltage-to-current converter, a sample-and-hold (S/H) circuit, a second voltage-to-current converter, and a signal generation circuit. The first voltage-to-current converter is coupled to remove a component of the output bus voltage sensed on the VBUS_IN pin from the voltage sensed on the SR-SNS pin. The S/H circuit is coupled to sample the voltage sensed on the SR-SNS pin and to provide a sampled voltage. The second voltage-to-current converter is coupled to convert the sampled voltage to a feed-forward current. The signal generation circuit is coupled to receive the feed-forward current and to generate feed-forward signals used to control operation of a primary side of the AC-DC converter.

Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. In an example embodiment, an integrated circuit (IC) controller for the secondary side of the AC-DC converter comprises a zero-crossing detector (ZCD) block and a negative-sensing (NSN) block coupled to a terminal. The terminal is configured to receive an input signal from a drain node of a SR circuit on the secondary side of the AC-DC converter. The ZCD block is configured to determine when a voltage of the input signal reaches 0V. The NSN block is configured to determine a negative voltage of the input signal. An internal rectifier, coupled between the terminal and local ground, is configured to ensure that substantially no current flows through the terminal during operation of the ZCD block and the NSN block.

Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC controller of the AC-DC converter includes a peak-detector block coupled to detect peak voltages sensed on a SR-SNS pin. The peak-detector block comprises a peak comparator, a sample-and-hold (S/H) circuit, and a DC offset circuit. The peak comparator is coupled to receive a sinusoidal input from the SR-SNS pin. The S/H circuit is coupled to sample the sinusoidal input and to provide a peak sampled voltage. The DC offset voltage circuit is coupled between the output of the S/H circuit and a reference voltage input of the peak comparator to subtract a DC offset voltage from the peak sampled voltage.

Abstract: Communicating fault indications between primary and secondary controller in a secondary-controlled flyback converter is described. In one embodiment, an apparatus includes a primary-side field effect transistor (FET) coupled to a flyback transformer coupled to the primary-side FET, and a primary-side controller coupled to the flyback transformer. The primary-side controller is configured to receive a signal from a secondary-side controller across a galvanic isolation barrier, apply a pulse signal to the primary-side FET in response to the signal to turn-on and turn-off the primary-side FET, communicate information to the secondary-side controller across the flyback transformer by varying a first pulse width of the pulse signal to a second pulse width and applying the pulse signal with the second pulse width to the primary-side FET.

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

Abstract: Controlling gate-source voltage with a gate driver in a secondary-side controller in a secondary-controlled converter is described. In one embodiment, an apparatus includes a provider field effect transistor (FET) coupled to a transformer and the secondary-side controller coupled to the transformer. The gate driver is integrated on the secondary-side controller and is configured to control the gate-source voltage and slew rate of the secondary-side FET.

Abstract: A secondary side controller for an AC-DC converter and method for operating the same are provided. Generally, the controller includes a single synchronous rectifier sense (SR-SNS) pin coupled to a drain of a SR on a secondary of a transformer to sense a voltage (VSRD). In feed-forward (FF) mode VSRD is a sum of a voltage (VIN) on a primary divided by a turn-ratio (N) of the transformer and an output bus voltage (VBUS). A voltage-to-current (V2I) converter coupled to the SR-SNS pin and to the output bus removes VBUS from VSRD. A sample and hold (S/H) module coupled to the SR-SNS pin samples a voltage (VSAMP) including information on VIN/N. A VIN/N V2I converter coupled to the S/H module converts VSAMP to a feed-forward current (IFF), and a cancellation and signal module coupled thereto extracts information on VIN from IFF and generates signals to control the AC-DC converter.

Abstract: An AC-DC converter with secondary side controller and synchronous rectifier (SR) architecture and method for operating the same are provided. Generally, the controller is implemented as an integrated circuit including a peak-detector module having a peak comparator with a first input coupled to a drain of the SR through a single SR sense (SR-SNS) pin to receive a sinusoidal input. A sample and hold (S/H) circuit with an input coupled to the SR-SNS pin samples the sinusoidal input and holds on an output of thereof a peak sampled voltage received on the input. A direct current (DC) offset voltage coupled between the output of the S/H circuit and the second input of the peak comparator subtracts an DC offset voltage from the peak sampled voltage to compensate for DC offset inaccuracies introduced by the S/H circuit and the peak comparator. Other embodiments are also disclosed.

Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. Generally, the secondary side controller includes a zero-crossing detector block, a negative-sensing block, a peak-detector block and a line-feed-forward block integrated in an integrated circuit (IC), and coupled to a secondary side of the converter through a single SR-sense (SR_SNS) pin through which the IC is coupled to a drain of the SR. The single SR_SNS pin has a maximum input voltage less than a rectified AC input voltage input to a secondary side of the converter, and, in one embodiment, is coupled to the drain of the SR through a voltage divider circuit including circuit elements both internal and external to the IC along with a rectifier element in series with the internal resistor.

Abstract: A dual protocol input device for use with a host system is provided. In one embodiment, the input device comprises a chip with a number of semiconductor devices integrally formed thereon, including: an optical navigation sensor (ONS) to sense movement of the ONS relative to a surface; a wired protocol block to communicate data from the ONS to the host system by a wired communication protocol; a wireless protocol block to communicate data from the ONS to the host system by a wireless communication protocol; and a micro-controller coupled to the ONS, the wired protocol block and the wireless protocol block, to switch the input device between the wireless communication protocol and the wired communication protocol.

Abstract: An improved buffer circuit and method for minimizing (or altogether eliminating) duty cycle distortion between input and output signals of the buffer circuit are provided herein. In general, the improved buffer circuit essentially decouples the charging and discharging current paths of the buffer circuit from a reference voltage supplied to the buffer circuit. This ensures substantially equal time delays between rising and falling edges of the input and output signals, thereby decreasing duty cycle distortion and maintaining a maximum operating frequency of the buffer circuit, even when the reference voltage approaches a transistor threshold voltage. In addition, the improved method may include forwarding an input signal with an input duty cycle onto mutually connected gate terminals of a pair of pull-down transistors, and activating/inactivating at least one of the pair of pull-down transistors during logic high and logic low voltage values of the input duty cycle, respectively.

Abstract: The apparatus includes a diode laser and a current source interconnected with the diode laser. Two independent circuits in the current source are configured to limit current flowing through the diode laser. A first current limiter circuit configured to limit a current output from the current source to an anode of the diode laser, and an independent second current limiter circuit configured to limit a current return from a cathode of the diode laser to the current source so that laser output power does not exceed a specified maximum regardless of a single fault in either the first or second current limiter circuits.

Abstract: Analog channel calibration methods, devices and systems are disclosed. One embodiment of the present invention pertains to a method for calibrating a channel offset of a current sensor which comprises measuring a channel offset native to a current sensor channel. The method also comprises storing the channel offset native to the current sensor channel to a register associated with the current sensor channel as a value. Additionally, the method comprises calibrating an output signal generated in response to an input signal to the current sensor channel based on the value.

Abstract: An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.

Abstract: A method and an apparatus are described for shorted input detection for amplifier circuits. An embodiment of a circuit includes multiple amplifier circuits, with each amplifier circuit having an input and an output. The circuit also includes multiple short detection circuits, with one of the short detection circuits being coupled to the input of each amplifier circuit. Each short detection circuit has an active state for detection of short circuits and an inactive state for normal amplifier operation. The circuit also includes a register coupled with the output of each of the amplifier circuits to hold the output of one or more of the amplifier circuits.

Abstract: A method and an apparatus are described for shorted input detection for amplifier circuits. An embodiment of a circuit includes multiple amplifier circuits, with each amplifier circuit having an input and an output. The circuit also includes multiple short detection circuits, with one of the short detection circuits being coupled to the input of each amplifier circuit. Each short detection circuit has an active state for detection of short circuits and an inactive state for normal amplifier operation. The circuit also includes a register coupled with the output of each of the amplifier circuits to hold the output of one or more of the amplifier circuits.

Abstract: One embodiment relates to an optical navigation apparatus which provides fault-tolerant limitation of laser output power. The apparatus includes a diode laser and a current source interconnected with the diode laser. Two independent circuits in the current source are configured to limit current flowing through the diode laser. Another embodiment relates to a method of providing fault-tolerant limitation of laser output power in an optical navigation apparatus. A first digital current limit value is converted to a first analog signal, and the first analog signal is used to limit an electrical current from a power supply connection to an anode of a diode laser. A second digital current limit value is converted to a second analog signal, and the second analog signal is used to limit an electrical current from a cathode of the diode laser to a ground connection. Other embodiments are also disclosed.

Abstract: An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.