Patents by Inventor Pulkit Shah
Pulkit Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10756644Abstract: Controlling gate-source voltage with a gate driver in a secondary-side controller in a secondary-controlled converter is described. In one embodiment, an apparatus includes a provider field effect transistor (FET) coupled to a transformer and the secondary-side controller coupled to the transformer. The gate driver is integrated on the secondary-side controller and is configured to control the gate-source voltage and slew rate of the secondary-side FET.Type: GrantFiled: September 16, 2019Date of Patent: August 25, 2020Assignee: Cypress Semiconductor CorporationInventor: Pulkit Shah
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Patent number: 10693384Abstract: A secondary side controller for an AC-DC converter and method for operating the same are provided. Generally, the controller includes a single synchronous rectifier sense (SR-SNS) pin coupled to a drain of a SR on a secondary of a transformer to sense a voltage (VSRD). In feed-forward (FF) mode VSRD is a sum of a voltage (VIN) on a primary divided by a turn-ratio (N) of the transformer and an output bus voltage (VBUS). A voltage-to-current (V2I) converter coupled to the SR-SNS pin and to the output bus removes VBUS from VSRD. A sample and hold (S/H) module coupled to the SR-SNS pin samples a voltage (VSAMP) including information on VIN/N. A VIN/N V2I converter coupled to the S/H module converts VSAMP to a feed-forward current (IFF), and a cancellation and signal module coupled thereto extracts information on VIN from IFF and generates signals to control the AC-DC converter.Type: GrantFiled: September 23, 2019Date of Patent: June 23, 2020Assignee: Cypress Semiconductor CorporationInventors: Partha Mondal, Hemant P. Vispute, Arun Khamesra, Hariom Rai, Pulkit Shah
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Patent number: 10651754Abstract: An AC-DC converter with secondary side controller and synchronous rectifier (SR) architecture and method for operating the same are provided. Generally, the controller is implemented as an integrated circuit including a peak-detector module having a peak comparator with a first input coupled to a drain of the SR through a single SR sense (SR-SNS) pin to receive a sinusoidal input. A sample and hold (S/H) circuit with an input coupled to the SR-SNS pin samples the sinusoidal input and holds on an output of thereof a peak sampled voltage received on the input. A direct current (DC) offset voltage coupled between the output of the S/H circuit and the second input of the peak comparator subtracts an DC offset voltage from the peak sampled voltage to compensate for DC offset inaccuracies introduced by the S/H circuit and the peak comparator. Other embodiments are also disclosed.Type: GrantFiled: September 23, 2019Date of Patent: May 12, 2020Assignee: Cypress Semiconductor CorporationInventors: Saravanan Murugesan, Karri Rajesh, Pulkit Shah, Arun Khamesra, Hariom Rai
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Patent number: 10554140Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. Generally, the secondary side controller includes a zero-crossing detector block, a negative-sensing block, a peak-detector block and a line-feed-forward block integrated in an integrated circuit (IC), and coupled to a secondary side of the converter through a single SR-sense (SR_SNS) pin through which the IC is coupled to a drain of the SR. The single SR_SNS pin has a maximum input voltage less than a rectified AC input voltage input to a secondary side of the converter, and, in one embodiment, is coupled to the drain of the SR through a voltage divider circuit including circuit elements both internal and external to the IC along with a rectifier element in series with the internal resistor.Type: GrantFiled: June 26, 2019Date of Patent: February 4, 2020Assignee: Cypress Semiconductor CorporationInventors: Arun Khamesra, Hariom Rai, Pulkit Shah
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Patent number: 8711096Abstract: A dual protocol input device for use with a host system is provided. In one embodiment, the input device comprises a chip with a number of semiconductor devices integrally formed thereon, including: an optical navigation sensor (ONS) to sense movement of the ONS relative to a surface; a wired protocol block to communicate data from the ONS to the host system by a wired communication protocol; a wireless protocol block to communicate data from the ONS to the host system by a wireless communication protocol; and a micro-controller coupled to the ONS, the wired protocol block and the wireless protocol block, to switch the input device between the wireless communication protocol and the wired communication protocol.Type: GrantFiled: March 27, 2009Date of Patent: April 29, 2014Assignee: Cypress Semiconductor CorporationInventors: Ke-Cai Zeng, Jonathan Young, Pulkit Shah, Yansun Xu, Eric Mann, Shankar Subramani
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Patent number: 8174291Abstract: An improved buffer circuit and method for minimizing (or altogether eliminating) duty cycle distortion between input and output signals of the buffer circuit are provided herein. In general, the improved buffer circuit essentially decouples the charging and discharging current paths of the buffer circuit from a reference voltage supplied to the buffer circuit. This ensures substantially equal time delays between rising and falling edges of the input and output signals, thereby decreasing duty cycle distortion and maintaining a maximum operating frequency of the buffer circuit, even when the reference voltage approaches a transistor threshold voltage. In addition, the improved method may include forwarding an input signal with an input duty cycle onto mutually connected gate terminals of a pair of pull-down transistors, and activating/inactivating at least one of the pair of pull-down transistors during logic high and logic low voltage values of the input duty cycle, respectively.Type: GrantFiled: June 24, 2004Date of Patent: May 8, 2012Assignee: Cypress Semiconductor CorporationInventors: Pulkit Shah, Gajendar Rohilla
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Patent number: 7809035Abstract: The apparatus includes a diode laser and a current source interconnected with the diode laser. Two independent circuits in the current source are configured to limit current flowing through the diode laser. A first current limiter circuit configured to limit a current output from the current source to an anode of the diode laser, and an independent second current limiter circuit configured to limit a current return from a cathode of the diode laser to the current source so that laser output power does not exceed a specified maximum regardless of a single fault in either the first or second current limiter circuits.Type: GrantFiled: May 12, 2006Date of Patent: October 5, 2010Assignee: Cypress Semiconductor CorporationInventors: Steven Sanders, Gary Gibbs, Ashish Pancholy, Gajender Rohilla, Pulkit Shah
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Patent number: 7755348Abstract: Analog channel calibration methods, devices and systems are disclosed. One embodiment of the present invention pertains to a method for calibrating a channel offset of a current sensor which comprises measuring a channel offset native to a current sensor channel. The method also comprises storing the channel offset native to the current sensor channel to a register associated with the current sensor channel as a value. Additionally, the method comprises calibrating an output signal generated in response to an input signal to the current sensor channel based on the value.Type: GrantFiled: March 28, 2009Date of Patent: July 13, 2010Assignee: Cypress Semiconductor CorporationInventors: Pulkit Shah, Gajender Rohilla
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Patent number: 7612585Abstract: An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.Type: GrantFiled: January 17, 2007Date of Patent: November 3, 2009Assignee: Cypress Semiconductor CorporationInventors: Pulkit Shah, Prasad Kotra
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Patent number: 7598812Abstract: A method and an apparatus are described for shorted input detection for amplifier circuits. An embodiment of a circuit includes multiple amplifier circuits, with each amplifier circuit having an input and an output. The circuit also includes multiple short detection circuits, with one of the short detection circuits being coupled to the input of each amplifier circuit. Each short detection circuit has an active state for detection of short circuits and an inactive state for normal amplifier operation. The circuit also includes a register coupled with the output of each of the amplifier circuits to hold the output of one or more of the amplifier circuits.Type: GrantFiled: June 12, 2007Date of Patent: October 6, 2009Assignee: Cypress Semiconductor CorporationInventors: Pulkit Shah, Gajender Rohilla
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Publication number: 20080001676Abstract: A method and an apparatus are described for shorted input detection for amplifier circuits. An embodiment of a circuit includes multiple amplifier circuits, with each amplifier circuit having an input and an output. The circuit also includes multiple short detection circuits, with one of the short detection circuits being coupled to the input of each amplifier circuit. Each short detection circuit has an active state for detection of short circuits and an inactive state for normal amplifier operation. The circuit also includes a register coupled with the output of each of the amplifier circuits to hold the output of one or more of the amplifier circuits.Type: ApplicationFiled: June 12, 2007Publication date: January 3, 2008Inventors: Pulkit Shah, Gajender Rohilla
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Publication number: 20070230525Abstract: One embodiment relates to an optical navigation apparatus which provides fault-tolerant limitation of laser output power. The apparatus includes a diode laser and a current source interconnected with the diode laser. Two independent circuits in the current source are configured to limit current flowing through the diode laser. Another embodiment relates to a method of providing fault-tolerant limitation of laser output power in an optical navigation apparatus. A first digital current limit value is converted to a first analog signal, and the first analog signal is used to limit an electrical current from a power supply connection to an anode of a diode laser. A second digital current limit value is converted to a second analog signal, and the second analog signal is used to limit an electrical current from a cathode of the diode laser to a ground connection. Other embodiments are also disclosed.Type: ApplicationFiled: May 12, 2006Publication date: October 4, 2007Inventors: Steven Sanders, Gary Gibbs, Ashish Pancholy, Gajender Rohilla, Pulkit Shah
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Publication number: 20070164804Abstract: An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.Type: ApplicationFiled: January 17, 2007Publication date: July 19, 2007Inventors: Pulkit Shah, Prasad Kotra
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Patent number: 6933786Abstract: An amplifier system has a control circuit. An amplifier is coupled to the control circuit and has a controllable gain. A controllable input impedance circuit is coupled to the control circuit. When the gain of the amplifier is changed the controllable input impedance circuit's impedance is adjusted, so that the input impedance to the system remains essentially constant.Type: GrantFiled: May 15, 2002Date of Patent: August 23, 2005Assignee: Cypress Semiconductor CorporationInventors: Palathol mana Sivadasan Mohandas, Gajender Rohilla, Pulkit Shah