Abstract: Embodiments disclosed herein include an integrated circuit structure. In an embodiment, the integrated circuit structure comprises an interlayer dielectric (ILD), and an opening in the ILD. In an embodiment, a first layer lines the opening, and a second layer lines the first layer. In an embodiment, the second layer comprises a semi-metal or transition metal dichalcogenide (TMD). The integrated circuit structure may further comprise a third layer over the second layer.

Abstract: An integrated circuit (IC) die includes a substrate and an array of memory cells formed in or on the substrate with a memory cell of the array of memory cells that includes a storage circuit that comprises a hysteretic-oxide material. A ternary content-addressable memory (TCAM) may utilize hysteretic-oxide memory cells. Other embodiments are disclosed and claimed.

Abstract: An integrated circuit die includes a first conductive structure for an input of a capacitively coupled device, a second conductive structure aligned with the first conductive structure for a signal to be capacitively coupled to the input of the capacitively coupled device, a first insulator material disposed between the first conductive structure and the second conductive structure, wherein the first insulator material comprises high gain insulator material, and a cooling structure operable to remove heat from the capacitively coupled device to achieve an operating temperature at or below 0° C. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a capacitor in the back-side layers of an IC die may comprise any type of solid-state electrolyte material disposed between electrodes of the capacitor. Another embodiment of a capacitor anywhere in an IC die may include one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride between electrodes of the capacitor. Other embodiments are disclosed and claimed.

Abstract: An integrated circuit (IC) die includes a plurality of front-side metallization layers including a first front-side metallization layer and one or more additional front-side metallization layers, a plurality of back-side metallization layers formed on the plurality front side metallization layers including a first back-side metallization layer and one or more additional back-side metallization layers, wherein the first front-side metallization layer is proximate to the first back-side metallization layer, and a vertical metallization structure formed through at least the first front-side metallization layer and the first back-side metallization layer, wherein the vertical metallization structure electrically connects a first metallization structure on one of the one or more additional front-side metallization layers to a second metallization structure on one of the one or more additional back-side metallization layers. Other embodiments are disclosed and claimed.

Abstract: Embodiments disclosed herein include through silicon waveguides and methods of forming such waveguides. In an embodiment, a through silicon waveguide comprises a substrate, where the substrate comprises silicon. In an embodiment, a waveguide is provided through the substrate. In an embodiment, the waveguide comprises a waveguide structure. and a cladding around the waveguide structure.

Abstract: An integrated circuit (IC) die includes a plurality of ferroelectric tunnel junction (FTJ) devices, where at least one FTJ of the plurality of FTJ devices comprises first electrode, a second electrode, ferroelectric material disposed between the first and second electrodes, and interface material disposed between at least one of the first and second electrodes and the ferroelectric material. Other embodiments are disclosed and claimed.

Abstract: An integrated circuit device includes a first IC die with a first front surface, a first back surface, and a first side surface along opposed edges of the first front surface and the first back surfaces of the first IC die, a second IC die with a second front surface, a second back surface, and a second side surface along opposed edges of the second front surface and second back surface of the second IC die, a substrate coupled to the first side surface of the first IC die and the second side surface of the second IC die, and fill material between one of the first front surface and the first back surface of the first IC die and one of the second front surface and second back surface of the second IC die. Other embodiments are disclosed and claimed.

Abstract: An integrated circuit (IC) die includes a first layer with conductive structures formed in a interlayer dielectric (ILD) material, with a portion of the conductive structures at a first surface of the first layer, a self-alignment layer in contact with non-conductive regions at the first surface of the first layer, a second layer with ILD material in contact with the self-alignment layer and the portion of the conductive structures at the first surface of the first layer, and conductive vias through the self-alignment layer and the second layer in contact with the portion of the conductive structures at the first surface of the first layer. The self-alignment layer may include a first material where the self-alignment layer is in contact with the conductive vias and a second material where the self-alignment layer is not in contact with the conductive vias. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an integrated circuit (IC) device may include a plurality of layers of wide bandgap (WBG)-based circuitry and a plurality of layers of silicon (Si)-based circuitry monolithically bonded to the plurality of layers of WBG-based circuitry, with one or more electrical connections between respective WBG-based circuits in the plurality of layers of WBG-based circuitry and Si-based circuits in the plurality of layers of Si-based circuitry. In some embodiments, a wafer-scale WBG-based IC is hybrid bonded or layer transfer bonded to a wafer-scale Si-based IC. Other embodiments are disclosed and claimed.

Abstract: Embodiments disclosed herein include a photonics module and methods of forming photonics modules. In an embodiment, the photonics module comprises a waveguide, and a modulator adjacent to the waveguide. In an embodiment, the modulator comprises a PN junction with a P-doped region and an N-doped region, where the PN junction is vertically oriented so that the P-doped region is over the N-doped region.

Abstract: An integrated circuit (IC) die includes a plurality of varactor devices, where at least one varactor of the plurality of varactor devices comprises a first electrode, a second electrode, and a multi-layer stack of ferroelectric material (e.g., ferroelectric variable capacitance material) disposed between the first and second electrodes. Other embodiments are disclosed and claimed.

Abstract: Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

Abstract: Structures having recessed channel transistors are described. In an example, an integrated circuit structure includes a channel structure having a recess extending partially there through. A gate dielectric layer is on a bottom and along sides of the recess, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below and uppermost surface of the channel structure.

Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.

Abstract: Structures having vertical transistors are described. In an example, an integrated circuit structure includes a channel structure on a drain contact layer, the channel structure having an opening extending there through. A gate dielectric layer is on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. A source contact layer is on sides of a portion of the gate dielectric layer extending above the channel structure.

Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Abstract: In one embodiment, a memory includes a die having: one or more memory layers having a plurality of banks to store data; and at least one other layer comprising at least one reconfigurable vector processor, the at least one reconfigurable vector processor to perform a vector computation on input vector data obtained from at least one bank of the plurality of banks and provide processed vector data to the at least one bank. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus comprises: a plurality of banks to store data; and a plurality of interconnects, each of the plurality of interconnects to couple a pair of the plurality of banks. In response to a data movement command, a first bank of the plurality of banks is to send data directly to a second bank of the plurality of banks via a first interconnect of the plurality of interconnects. Other embodiments are described and claimed.

Abstract: Integrated circuit (IC) including transistors with high-mobility/high-saturation velocity, non-silicon channel materials coupled to a silicon substrate through counter-doped sub-channel materials, which greatly reduce electrical leakage currents through the substrate when the IC is operated at very low temperatures (e.g., below ?25 C). With low temperature operation, high transistor performance associated with the non-silicon channel materials can be integrated into high density IC architectures that avoid the limitations associated with semiconductor material layer transfers.