Abstract: In one embodiment, an apparatus includes a first die adapted on a second die. The first die may have a plurality of cores, each of the plurality of cores associated with a first plurality of through silicon vias (TSVs), and the second die may have dynamic random access memory (DRAM). The DRAM of the second die may have a plurality of local portions, each of the plurality of local portions associated with a second plurality of TSVs, where each of at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by the corresponding first and second plurality of TSVs. Other embodiments are described and claimed.

Abstract: Integrated circuits including static random-access memory (SRAM) bit-cells that are actively cooled to a low temperature (e.g., in the cryogenic range) where transistor drive currents become significantly increased and transistor leakage currents significantly reduced. With the drive current improvement, bit-cell capacitance may be reduced by defining narrower transistor fin structures and/or four transistor (4T) bit-cells may be implemented, for example with two parallel transistor fins and colinear gate electrodes.

Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.

Abstract: Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

Abstract: Methods and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). In one embodiment, the integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device.

Abstract: In one embodiment, a memory comprises: a first subarray having a first plurality of memory cells, the first subarray having a first orientation; and a second subarray having a second plurality of memory cells, the second subarray having a second orientation, the second orientation orthogonal to the first orientation. Other embodiments are described and claimed.

Abstract: Integrated circuit dies, systems, and techniques, are described herein related to single conductivity type transistor circuits operable at low temperatures. A system includes a functional circuit block of an integrated circuit die having a number of non-planar transistors all of the same conductivity type. The system further includes cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.

Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Abstract: Techniques and mechanisms for an integrated circuit (IC) die to provide electrical coupling across active layers. In an embodiment, an IC die comprises a first active layer, a second active layer, first metallization layers between the first and second active layers, and second metallization layers on the second active layer. A via structure extends through one or more of the second metallization layers, and further through the second active layer and the first metallization layers, to a side of the first active layer. The via structure is electrically coupled to a first interconnect structure of the second metallization layers and a second interconnect structure which is on an opposite side of the first active layer. In another embodiment, a distal end of the via structure adjoins multiple vias which each extend from the second interconnect structure and at least partially through the first active layer.

Abstract: Techniques and mechanisms to facilitate a conduction of heat across one or more active layers of an integrated circuit (IC) die. In an embodiment, an IC die comprises vertically stacked active layers, where metallization layers are variously disposed on opposite sides of a first such active layer. A thermal channel structure of the IC die extends through said first active layer, and through the metallization layers, to each of two thermally conductive material layers. Thermal interface structures are variously disposed each between a different respective distal end of the thermal channel structure and a different respective one of the thermally conductive material layers. In another embodiment, the thermal channel structure comprises a substantially columnar main body portion, which is electrically coupled to one or more interconnect structures of the metallization layers.

Abstract: Techniques and mechanisms for an integrated circuit (IC) die structure to comprise heterogeneous active layers which are stacked with each other to form structures of respective memory arrays. In an embodiment, an IC die structure comprises first metal oxide semiconductor field effect transistors (MOSFETs) of a first active layer, and second MOSFETs of a second active layer which is vertically stacked with the first active layer. A first memory array comprises the first MOSFETs, and a second memory array comprises the second MOSFETs. The first memory array comprises a four transistor (4T) static random access memory (SRAM) cell, each transistor of which corresponds to a first dopant type. The second memory array comprises a second memory cell, each transistor of which corresponds to a second dopant type. In another embodiment, a cell density of the first memory array is substantially less than that of the second memory array.

Abstract: Techniques and mechanisms for an integrated circuit (IC) die structure to comprise heterogeneous active layers which are variously stacked in respective face-to-back arrangements. In an embodiment, three active layers each correspond to a different respective transistor type, wherein two active layers comprise transistors of respective memory arrays, and a third active layer comprises transistors of circuitry which is coupled to access the memory arrays. In another embodiment, hybrid bond structures are disposed between two of the active layers.

Abstract: Integrated circuit interconnect structures including an interconnect metallization feature comprising a sidewall reacted with a chalcogen into a low resistance liner. A portion of a backbone material or a metal seed layer may be advantageously converted into a metal chalcogenide, which can lower scattering resistance of an interconnect feature relative to alternative diffusion barrier materials, such a tantalum. Scattering resistance of such metal chalcogenide liner materials may be further reduced by actively cooling an IC, for example to cryogenic temperatures.

Abstract: In one embodiment, an apparatus comprises: a plurality of banks to store data; and a plurality of interconnects, each of the plurality of interconnects to couple a pair of the plurality of banks. In response to a data movement command, a first bank of the plurality of banks is to send data directly to a second bank of the plurality of banks via a first interconnect of the plurality of interconnects. Other embodiments are described and claimed.

Abstract: Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. For example, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, and both first and second arrays to store data of a processor. The second plurality of memory cells implements a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit is to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.

Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Abstract: In one embodiment, an integrated circuit package includes: a first die having a plurality of cores, each of the plurality of cores having a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM); and a second die comprising the DRAM, where at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die. Other embodiments are described and claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that include DRAM using wide band gap materials, such as SiC or GaN to reduce transistor leakage. In addition, transistors may be fabricated adding one or more extra layers between a source and a drain of a transistor and the contact of the source of the drain to increase the effective electrical gate length of the transistor to further reduce leakage. In addition, for these transistors, a thickness of the body below the gate may be made narrow to improve gate control. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use high voltage transistors within a SiC layer that are coupled with one or more transistors in one or more other layers in a cascode format in order to switch the high voltage transistors in the SiC layer using low voltages. Other embodiments may be described and/or claimed.

Abstract: In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).