Patents by Inventor Pushkar Ranade

Pushkar Ranade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9006843
    Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: April 14, 2015
    Assignee: SuVolta, Inc.
    Inventors: Pushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
  • Patent number: 8999861
    Abstract: A method for fabricating a semiconductor structure so as to have reduced junction leakage is disclosed. The method includes providing substitutional boron in a semiconductor substrate. The method includes preparing the substrate using a pre-amorphization implant and a carbon implant followed by a recrystallization step and a separate defect repair/activation step. Boron is introduced to the pre-amorphized region preferably by ion implantation.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 7, 2015
    Assignee: SuVolta, Inc.
    Inventors: Lance Scudder, Pushkar Ranade, Charles Stager, Lucian Shifren, Dalong Zhao, U.C. Sridharan, Michael Duane
  • Publication number: 20150061012
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Application
    Filed: November 6, 2014
    Publication date: March 5, 2015
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Patent number: 8963249
    Abstract: A field effect transistor having a source, drain, and a gate can include a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried insulator layer; a low dopant channel region positioned below the gate and between the source and the drain and in an upper portion of the semiconductor overlayer; and a plurality of doped regions having a predetermined dopant concentration profile, including a screening region positioned in the semiconductor overlayer below the low dopant channel region, the screening region extending toward the buried insulator layer, and a threshold voltage set region positioned between the screening region and the low dopant channel, the screening region and the threshold voltage set region having each a peak dopant concentration, the threshold voltage region peak dopant concentration being between 1/50 and ½ of the peak dopant concentration of the screening region.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 24, 2015
    Assignee: Suvolta, Inc.
    Inventors: Lucian Shifren, Pushkar Ranade
  • Patent number: 8937005
    Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 20, 2015
    Assignee: SuVolta, Inc.
    Inventors: Lance S. Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
  • Patent number: 8916937
    Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: December 23, 2014
    Assignee: SuVOLTA, Inc.
    Inventors: Thomas Hoffmann, Pushkar Ranade, Lucian Shifren, Scott E. Thompson
  • Patent number: 8883600
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 11, 2014
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Patent number: 8877619
    Abstract: Structures and processes are provided that can be used for effectively integrating different transistor designs across a process platform. In particular, a bifurcated process is provided in which dopants and other processes for forming some transistor types may be performed prior to STI or other device isolation processes, and other devices may be formed thereafter. Thus, doping and other steps and their sequence with respect to the STI process can be selected to be STI-first or STI-last, depending on the device type to be manufactured, the range of device types that are manufactured on the same wafer or die, or the range of device types that are planned to be manufactured using the same or similar mask sets.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 4, 2014
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Lance Scudder, Dalong Zhao, Teymur Bakhisher, Sameer Pradhan
  • Patent number: 8858818
    Abstract: The effects of knock-on oxide in a semiconductor substrate are reduced by providing a semiconductor substrate and forming a thin layer of native oxide on the semiconductor substrate. Ion implantation is performed through the native oxide layer. The native oxide layer reduces the phenomenon of knock-on oxide and oxygen concentration within the semiconductor substrate. Further reduction may be achieved by etching the surface of the semiconductor substrate in order to eliminate a concentration of oxygen at a surface of the semiconductor substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: October 14, 2014
    Assignee: SuVolta, Inc.
    Inventors: Pushkar Ranade, Toshifumi Mori, Ken-ichi Okabe, Toshiki Miyake
  • Publication number: 20140284722
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD, so that the body bias can be tuned separately from VT for a given device.
    Type: Application
    Filed: June 5, 2014
    Publication date: September 25, 2014
    Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve
  • Patent number: 8796048
    Abstract: The present disclosure provides methods and structures for measurement, control, and monitoring the thickness of thin film layers formed as part of a semiconductor manufacturing process. The methods and structures presented provide the capability to measure and monitor the thickness of the thin film using trench line structures. In certain embodiments, the thin film thickness measurement system can be integrated with thin film growth and control software, providing automated process control (APC) or statistical process control (SPC) capability by measuring and monitoring the thin film thickness during manufacturing. Methods for measuring the thickness of thin films can be important to the fabrication of integrated circuits because the thickness and uniformity of the thin film can determine electrical characteristics of the transistors being fabricated.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: August 5, 2014
    Assignee: Suvolta, Inc.
    Inventors: Scott E. Thompson, Pushkar Ranade, Lance Scudder, Charles Stager
  • Patent number: 8778786
    Abstract: Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: July 15, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lance Scudder, Pushkar Ranade, Dalong Zhao, Teymur Bakhishev, Urupattur C. Sridharan, Taiji Ema, Toshifumi Mori, Mitsuaki Hori, Junji Oh, Kazushi Fujita, Yasunobu Torii
  • Patent number: 8759872
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD, so that the body bias can be tuned separately from VT for a given device.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: June 24, 2014
    Assignee: SuVolta, Inc.
    Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve
  • Publication number: 20140167157
    Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: SuVolta, Inc.
    Inventors: Pushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
  • Publication number: 20140167156
    Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: SuVolta, lnc.
    Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
  • Patent number: 8748986
    Abstract: Structures and methods of fabrication thereof related to an improved semiconductor on insulator (SOI) transistor formed on an SOI substrate. The improved SOI transistor includes a substantially undoped channel extending between the source and the drain, an optional threshold voltage set region positioned below the substantially undoped channel, and a screening region positioned below the threshold voltage set region. The threshold voltage of the improved SOI transistor can be adjusted without halo implants or threshold voltage implants into the channel, using the position and/or dopant concentration of the screening region and/or the threshold voltage set region.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: June 10, 2014
    Assignee: Suvolta, Inc.
    Inventors: Lucian Shifren, Pushkar Ranade
  • Patent number: 8735987
    Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: May 27, 2014
    Assignee: Suvolta, Inc.
    Inventors: Thomas Hoffmann, Scott E. Thompson, Pushkar Ranade
  • Publication number: 20140103406
    Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.
    Type: Application
    Filed: December 19, 2013
    Publication date: April 17, 2014
    Inventors: Lingquan Wang, Teymur Bakhishev, Dalong Zhao, Pushkar Ranade, Sameer Pradhan, Thomas Hoffmann, Lucian Shifren, Lance Scudder
  • Patent number: 8686511
    Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3?, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: April 1, 2014
    Assignee: SuVolta, Inc.
    Inventors: Pushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
  • Publication number: 20140084385
    Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 27, 2014
    Applicant: SuVolta, Inc.
    Inventors: Thomas Hoffmann, Lucian Shifren, Scott E. Thompson, Pushkar Ranade, Jing Wang, Paul E. Gregory, Sachin R. Sonkusale, Lance Scudder, Dalong Zhao, Teymur Bakhishev, Yujie Liu, Lingquan Wang, Weimin Zhang, Sameer Pradhan, Michael Duane, Sung Hwan Kim