Abstract: An integrated circuit (IC) die includes a first layer with conductive structures formed in a interlayer dielectric (ILD) material, with a portion of the conductive structures at a first surface of the first layer, a self-alignment layer in contact with non-conductive regions at the first surface of the first layer, a second layer with ILD material in contact with the self-alignment layer and the portion of the conductive structures at the first surface of the first layer, and conductive vias through the self-alignment layer and the second layer in contact with the portion of the conductive structures at the first surface of the first layer. The self-alignment layer may include a first material where the self-alignment layer is in contact with the conductive vias and a second material where the self-alignment layer is not in contact with the conductive vias. Other embodiments are disclosed and claimed.

Abstract: An integrated circuit (IC) die includes a plurality of varactor devices, where at least one varactor of the plurality of varactor devices comprises a first electrode, a second electrode, and a multi-layer stack of ferroelectric material (e.g., ferroelectric variable capacitance material) disposed between the first and second electrodes. Other embodiments are disclosed and claimed.

Abstract: Embodiments disclosed herein include through silicon waveguides and methods of forming such waveguides. In an embodiment, a through silicon waveguide comprises a substrate, where the substrate comprises silicon. In an embodiment, a waveguide is provided through the substrate. In an embodiment, the waveguide comprises a waveguide structure. and a cladding around the waveguide structure.

Abstract: An integrated circuit device includes a first IC die with a first front surface, a first back surface, and a first side surface along opposed edges of the first front surface and the first back surfaces of the first IC die, a second IC die with a second front surface, a second back surface, and a second side surface along opposed edges of the second front surface and second back surface of the second IC die, a substrate coupled to the first side surface of the first IC die and the second side surface of the second IC die, and fill material between one of the first front surface and the first back surface of the first IC die and one of the second front surface and second back surface of the second IC die. Other embodiments are disclosed and claimed.

Abstract: Structures having vertical transistors are described. In an example, an integrated circuit structure includes a channel structure on a drain contact layer, the channel structure having an opening extending there through. A gate dielectric layer is on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. A source contact layer is on sides of a portion of the gate dielectric layer extending above the channel structure.

Abstract: Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.

Abstract: Structures having recessed channel transistors are described. In an example, an integrated circuit structure includes a channel structure having a recess extending partially there through. A gate dielectric layer is on a bottom and along sides of the recess, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below and uppermost surface of the channel structure.

Abstract: In one embodiment, an apparatus comprises: a plurality of banks to store data; and a plurality of interconnects, each of the plurality of interconnects to couple a pair of the plurality of banks. In response to a data movement command, a first bank of the plurality of banks is to send data directly to a second bank of the plurality of banks via a first interconnect of the plurality of interconnects. Other embodiments are described and claimed.

Abstract: In one embodiment, a memory includes a die having: one or more memory layers having a plurality of banks to store data; and at least one other layer comprising at least one reconfigurable vector processor, the at least one reconfigurable vector processor to perform a vector computation on input vector data obtained from at least one bank of the plurality of banks and provide processed vector data to the at least one bank. Other embodiments are described and claimed.

Abstract: Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. In one embodiment, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, both first and second arrays to store data of a processor, the second plurality of memory cells implementing a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.

Abstract: Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.

Abstract: Method and apparatus to implement an integrated circuit (IC) device to perform homomorphic computing. In one embodiment, the IC device includes a memory array containing a plurality of memory cells to store data and compute circuitry to perform computations on encrypted data stored in the memory array. The memory array and the compute circuitry are integrated in a same die but at different die depth. At least a portion of the memory array overlaps a portion of the compute circuitry in a same x-y plane.

Abstract: Methods and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). In one embodiment, the integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device.

Abstract: In one embodiment, an apparatus includes a first die adapted on a second die. The first die may have a plurality of cores, each of the plurality of cores associated with a first plurality of through silicon vias (TSVs), and the second die may have dynamic random access memory (DRAM). The DRAM of the second die may have a plurality of local portions, each of the plurality of local portions associated with a second plurality of TSVs, where each of at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by the corresponding first and second plurality of TSVs. Other embodiments are described and claimed.

Abstract: Integrated circuit interconnect structures including an interconnect metallization feature comprising a sidewall reacted with a chalcogen into a low resistance liner. A portion of a backbone material or a metal seed layer may be advantageously converted into a metal chalcogenide, which can lower scattering resistance of an interconnect feature relative to alternative diffusion barrier materials, such a tantalum. Scattering resistance of such metal chalcogenide liner materials may be further reduced by actively cooling an IC, for example to cryogenic temperatures.

Abstract: Integrated circuit (IC) including transistors with high-mobility/high-saturation velocity, non-silicon channel materials coupled to a silicon substrate through counter-doped sub-channel materials, which greatly reduce electrical leakage currents through the substrate when the IC is operated at very low temperatures (e.g., below ?25 C). With low temperature operation, high transistor performance associated with the non-silicon channel materials can be integrated into high density IC architectures that avoid the limitations associated with semiconductor material layer transfers.

Abstract: Systems and techniques related to narrow interconnects for integrated circuits. An integrated circuit die includes narrow interconnect lines with a relatively high pitch. A system includes an integrated circuit die with narrow interconnect lines and cooling structure to lower an operating temperature of at least the interconnects to a point where conductance of the narrow interconnect is sufficient.

Abstract: Method and apparatus to implement an integrated circuit (IC) device to perform compression/decompression operations. In one embodiment, the IC device includes a memory array containing a plurality of memory cells to store data and compression/decompression circuitry to perform compression operations on data to be written to the memory array and decompression operations on data read from the memory array. The memory array and the compression/decompression circuitry are integrated in a same die but at different die depth. At least a portion of the memory array overlaps a portion of the compression/decompression circuitry in a same x-y plane.