Abstract: Integrated circuit interconnect structures including an interconnect metallization feature comprising a sidewall reacted with a chalcogen into a low resistance liner. A portion of a backbone material or a metal seed layer may be advantageously converted into a metal chalcogenide, which can lower scattering resistance of an interconnect feature relative to alternative diffusion barrier materials, such a tantalum. Scattering resistance of such metal chalcogenide liner materials may be further reduced by actively cooling an IC, for example to cryogenic temperatures.

Abstract: Method and apparatus to implement an integrated circuit (IC) device to perform homomorphic computing. In one embodiment, the IC device includes a memory array containing a plurality of memory cells to store data and compute circuitry to perform computations on encrypted data stored in the memory array. The memory array and the compute circuitry are integrated in a same die but at different die depth. At least a portion of the memory array overlaps a portion of the compute circuitry in a same x-y plane.

Abstract: Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.

Abstract: In one embodiment, a memory comprises: a first subarray having a first plurality of memory cells, the first subarray having a first orientation; and a second subarray having a second plurality of memory cells, the second subarray having a second orientation, the second orientation orthogonal to the first orientation. Other embodiments are described and claimed.

Abstract: Integrated circuits including static random-access memory (SRAM) bit-cells that are actively cooled to a low temperature (e.g., in the cryogenic range) where transistor drive currents become significantly increased and transistor leakage currents significantly reduced. With the drive current improvement, bit-cell capacitance may be reduced by defining narrower transistor fin structures and/or four transistor (4T) bit-cells may be implemented, for example with two parallel transistor fins and colinear gate electrodes.

Abstract: Integrated circuit dies, systems, and techniques, are described herein related to single conductivity type transistor circuits operable at low temperatures. A system includes a functional circuit block of an integrated circuit die having a number of non-planar transistors all of the same conductivity type. The system further includes cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.

Abstract: Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. In one embodiment, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, both first and second arrays to store data of a processor, the second plurality of memory cells implementing a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.

Abstract: Systems and techniques related to narrow interconnects for integrated circuits. An integrated circuit die includes narrow interconnect lines with a relatively high pitch. A system includes an integrated circuit die with narrow interconnect lines and cooling structure to lower an operating temperature of at least the interconnects to a point where conductance of the narrow interconnect is sufficient.

Abstract: Method and apparatus to implement an integrated circuit (IC) device to perform compression/decompression operations. In one embodiment, the IC device includes a memory array containing a plurality of memory cells to store data and compression/decompression circuitry to perform compression operations on data to be written to the memory array and decompression operations on data read from the memory array. The memory array and the compression/decompression circuitry are integrated in a same die but at different die depth. At least a portion of the memory array overlaps a portion of the compression/decompression circuitry in a same x-y plane.

Abstract: Methods and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). In one embodiment, the integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device.

Abstract: In one embodiment, an apparatus includes: at least one core to execute operations on data; a cryptographic circuit to perform cryptographic operations; a static random access memory (SRAM) coupled to the at least one core; and a ferroelectric memory coupled to the at least one core. In response to a read request, the SRAM is to provide an encryption key to the cryptographic circuit and the ferroelectric memory is to provide encrypted data to the cryptographic circuit, the encryption key associated with the encrypted data. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes a first die adapted on a second die. The first die may have a plurality of cores, each of the plurality of cores associated with a first plurality of through silicon vias (TSVs), and the second die may have dynamic random access memory (DRAM). The DRAM of the second die may have a plurality of local portions, each of the plurality of local portions associated with a second plurality of TSVs, where each of at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by the corresponding first and second plurality of TSVs. Other embodiments are described and claimed.

Abstract: In one embodiment, an integrated circuit package includes: a first die having a plurality of cores, each of the plurality of cores having a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM); and a second die comprising the DRAM, where at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die. Other embodiments are described and claimed.

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power. Based on the differences in the memory, the memory controller can manage access to the memory device with adjusted control parameters based on lower leakage voltage for the memory cells and lower line resistance for the memory array.

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power.

Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.