Patents by Inventor Pushkar Ranade

Pushkar Ranade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230317605
    Abstract: Systems and techniques related to narrow interconnects for integrated circuits. An integrated circuit die includes narrow interconnect lines with a relatively high pitch. A system includes an integrated circuit die with narrow interconnect lines and cooling structure to lower an operating temperature of at least the interconnects to a point where conductance of the narrow interconnect is sufficient.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Wilfred Gomes, Pushkar Ranade, Sagar Suthram, Rajabali Koduri
  • Publication number: 20230317557
    Abstract: Integrated circuit dies, systems, and techniques, are described herein related to single conductivity type transistor circuits operable at low temperatures. A system includes a functional circuit block of an integrated circuit die having a number of non-planar transistors all of the same conductivity type. The system further includes cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Abhishek Sharma, Wilfred Gomes, Pushkar Ranade, Sagar Suthram, Rajabali Koduri, Anand Murthy, Tahir Ghani
  • Publication number: 20230318825
    Abstract: In one embodiment, an apparatus includes: at least one core to execute operations on data; a cryptographic circuit to perform cryptographic operations; a static random access memory (SRAM) coupled to the at least one core; and a ferroelectric memory coupled to the at least one core. In response to a read request, the SRAM is to provide an encryption key to the cryptographic circuit and the ferroelectric memory is to provide encrypted data to the cryptographic circuit, the encryption key associated with the encrypted data. Other embodiments are described and claimed.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Abhishek Anil Sharma, Sagar Suthram, Pushkar Ranade, Wilfred Gomes
  • Publication number: 20230317794
    Abstract: Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Wilfred Gomes, Sagar Suthram, Pushkar Ranade, Rajabali Koduri
  • Patent number: 10325986
    Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: June 18, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
  • Patent number: 10217838
    Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: February 26, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
  • Publication number: 20180261683
    Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.
    Type: Application
    Filed: April 26, 2018
    Publication date: September 13, 2018
    Applicant: Mie Fujitsu Semiconductor Limited
    Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
  • Patent number: 10014387
    Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: July 3, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
  • Patent number: 9991300
    Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: June 5, 2018
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
  • Patent number: 9922977
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT (variation in VT) compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD (the operating voltage supplied to the transistor), so that the body bias can be tuned separately from VT for a given device.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 20, 2018
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve
  • Patent number: 9865596
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: January 9, 2018
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang
  • Patent number: 9847420
    Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventor: Pushkar Ranade
  • Publication number: 20170323916
    Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
    Type: Application
    Filed: July 25, 2017
    Publication date: November 9, 2017
    Inventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
  • Patent number: 9812550
    Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: November 7, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
  • Patent number: 9793172
    Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: October 17, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lance Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
  • Patent number: 9786703
    Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: October 10, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
  • Publication number: 20170207336
    Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.
    Type: Application
    Filed: March 29, 2017
    Publication date: July 20, 2017
    Inventor: Pushkar Ranade
  • Publication number: 20170141209
    Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
  • Patent number: 9646822
    Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventor: Pushkar Ranade
  • Publication number: 20170062593
    Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.
    Type: Application
    Filed: November 14, 2016
    Publication date: March 2, 2017
    Inventor: Pushkar Ranade