Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may identify a first timer associated with a first antenna and a second timer associated with a second antenna. The UE may identify an expiration of the first timer associated with the first antenna. The UE may determine, based at least in part on the identified expiration of the first timer, whether a remaining time of the second timer associated with the second antenna is less than a timer threshold. The UE may select, based at least in part on the determination that the remaining time of the second timer is less than the timer threshold, the second antenna. Numerous other aspects are provided.

Abstract: Methods, systems, and devices for operating an amplifier with a controllable pull-down capability are described. A memory device may include a memory array and a power circuit that generates an internal signal for components in the memory array. The power circuit may include an amplifier and a power transistor that is coupled with the amplifier. A pull-down capability of the amplifier may be controllable using an external signal that is based on a difference between a reference signal and the internal signal. The power circuit may also include a comparator that is coupled with the amplifier and configured to compare the reference signal and the internal signal. Components of the comparator may be integrated with components of the amplifier, may share a bias circuit, and may use nodes within the amplifier to control the comparator. A signal output by the comparator may control the pull-down capability of the amplifier.

Abstract: The present disclosure provides a method and apparatus for assigning a task. The method may include: generating a testing task list based on a received testing task request, the testing task list including at least one testing task; acquiring a currently assigned task of at least one terminal; and adopting, in response to calculating load information of the currently assigned task executed by all terminals, a different task assignment rule based on the load information to assign a testing task in the testing task list to each terminal, the load information including an estimated time consumption and an amount of generated data of the currently assigned task executed by the respective terminals.

Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.

Abstract: A memory device includes a voltage generator configured to generate a reference voltage for transmission to at least one component of the memory device. The voltage generator includes a first input to receive a first signal having a first voltage value. The voltage generator also includes a second input to receive a second signal having a second voltage value. The voltage generator further includes a first circuit configured to generate third voltage and a second circuit coupled to the first circuit to receive the third voltage value, wherein the second circuit receives the first signal and the second signal and is configured to utilize the third voltage value to facilitate comparison of the first voltage value and the second voltage value to generate an output voltage.

Abstract: The present disclosure is directed to methods reagents and kits for solid phase extraction, derivatization with crown ether containing derivatizing agents, and mass spectrometry of the derivatized analytes.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first interconnect layer including first interconnects is formed above a first substrate. A first bonding layer including first bonding contacts is formed above the first interconnect layer, such that each first interconnect is in contact with a respective first bonding contact. A second interconnect layer including second interconnects is formed above a second substrate. A second bonding layer including second bonding contacts is formed above the second interconnect layer, such that at least one second bonding contact is in contact with a respective second interconnect, and at least another second bonding contact is separated from the second interconnects. The first and second substrates are bonded in a face-to-face manner, such that each first bonding contact is in contact with one second bonding contact at a bonding interface.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may perform a fast antenna switched diversity evaluation by obtaining at least two signal measurements for each transmit antenna of the UE based at least in part on detecting one or more triggering conditions for switching one or more transmit antennas of the UE. The UE may switch the one or more transmit antennas based at least in part on the at least two signal measurements for each transmit antenna. Numerous other aspects are described.

Abstract: The present disclosure relates to a method and a device for monitoring the water volume change, and a computer device and a storage medium. The method includes: acquiring a lake shoreline change sequence, a lake area change sequence, and a combined altimetry water level sequence; obtaining a lake water level sequence based on the combined altimetry water level sequence and the lake shoreline change sequence; calculating a first regressive relationship between the lake water volume and the lake water level based on the lake area change sequence and the lake water level sequence; and obtaining a lake water volume change sequence based on the lake water level sequence and the first regressive relationship between the lake water volume and the lake water level.

Abstract: An exemplary method for processing a corresponding service based on an event detected at a physical device using a blockchain includes receiving an event model identifier and data of an event, wherein the event model identifier indicates an event model for describing the event, and the data comprises one or more parameters in the event model; determining a contract identifier associated with the event model identifier based on a predetermined relationship between the event model identifier and the contract identifier; identifying a smart contract in a blockchain network based on the contract identifier; and sending a request that invokes the smart contract to a first node in the blockchain network based on the contract identifier and that causes each node in the blockchain network to invoke the smart contract based on the data to perform service processing logic corresponding to the smart contract.

Abstract: Methods, systems, and devices for operating an amplifier with a controllable pull-down capability are described. A memory device may include a memory array and a power circuit that generates an internal signal for components in the memory array. The power circuit may include an amplifier and a power transistor that is coupled with the amplifier. A pull-down capability of the amplifier may be controllable using an external signal that is based on a difference between a reference signal and the internal signal. The power circuit may also include a comparator that is coupled with the amplifier and configured to compare the reference signal and the internal signal. Components of the comparator may be integrated with components of the amplifier, may share a bias circuit, and may use nodes within the amplifier to control the comparator. A signal output by the comparator may control the pull-down capability of the amplifier.

Abstract: In an embodiment, a server receives—a digital key request for a digital key to unlock a smart lock. A biometric feature request for collecting a biometric feature from the mobile device is generated and sent to the mobile device. A biometric feature corresponding to the biometric feature request is received. Identity information and a device identifier of the smart lock is received from another server. Based on the identity information, a matching biometric feature stored in a biometric feature database is determined. An identity of a user corresponding to the received biometric feature is verified based on the matching biometric feature. After the identity of the user is verified, smart lock information is identified. A digital key for unlocking the smart lock is generated based on the digital key request and the smart lock information and sent to the mobile device.

Abstract: A video abstract generation method is provided. The method includes obtaining a target searching condition; searching a video database for structured image data meeting the target searching condition, the structured image data being stored in the video database in a structured data format; and performing video synthesis on the structured image data meeting the target searching condition, to generate a video abstract.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an array well structure in a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one vertical through contact in the periphery region and in contact with the array well structure. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the array well structure, and in contact with the at least one vertical through contact.

Abstract: An optical fiber connector is provided. The optical fiber connector comprises a plastic housing. The optical fiber connector comprises a metallic clip. The plastic housing is adapted to connect the optical fiber connector to an optical fiber adapter. The metallic clip is arranged at a side of the plastic housing. The metallic clip extends from the plastic housing. The metallic clip is adapted to press against a metallic part of the optical fiber adapter.

Abstract: Devices for generating a delay output signal are disclosed. A device may include a first delay circuit and a second delay circuit coupled in series between a first node and a second node in a delay path for the device, and having a third node therebetween. The device may also include a third circuit coupled to the third node and configured to charge the third node responsive to detecting a signal has passed through the first node and the third node. Associated semiconductor devices and methods are also disclosed.

Abstract: Methods, systems, and devices for timing signal delay for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. A memory device may include delay components having a configurable impedance based at least in part on one or more fabrication characteristics of the memory device, one or more operating conditions of the memory device, one or more bias voltages, or a combination thereof.

Abstract: Methods, systems, and devices for timing signal delay for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. A memory device may include delay components having a configurable impedance based at least in part on one or more fabrication characteristics of the memory device, one or more operating conditions of the memory device, one or more bias voltages, or a combination thereof.

Abstract: A construction method for a shallow-buried multi-arch tunnel under water-rich geological conditions includes the following steps: cleaning a grouting ground surface; marking a grouting reinforcement scope; performing survey setting-out; drawing a cross-section diagram to scale; calculating out coordinates and angles of anchor points that need to be set; marking drilling positions; nailing small wooden piles at the drilling positions for identifying; determining a setting depth of the anchor rods according to ground elevation; drilling holes, cleaning bottom of hole, grouting, performing construction preparation, performing long pipe shed construction at the entrance after an earth-rock of a tunnel entrance and an open cut tunnel is excavated to flush with a springing line of the tunnel. A down-the-hole drill is used for drilling in construction. Long pipe shed grouting is designed based on solidifying a soil mass in limited scope around a consolidation pipe shed.