Patents by Inventor Qi Huang

Qi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210319816
    Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.
    Type: Application
    Filed: April 8, 2020
    Publication date: October 14, 2021
    Inventors: Zhi Qi Huang, Wei Lu Chu, Dong Pan
  • Publication number: 20210314136
    Abstract: An exemplary method for processing a corresponding service based on an event detected at a physical device using a blockchain includes receiving an event model identifier and data of an event, wherein the event model identifier indicates an event model for describing the event, and the data comprises one or more parameters in the event model; determining a contract identifier associated with the event model identifier based on a predetermined relationship between the event model identifier and the contract identifier; identifying a smart contract in a blockchain network based on the contract identifier; and sending a request that invokes the smart contract to a first node in the blockchain network based on the contract identifier and that causes each node in the blockchain network to invoke the smart contract based on the data to perform service processing logic corresponding to the smart contract.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Applicant: ALIPAY (HANGZHOU) INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Qi Huang
  • Patent number: 11113914
    Abstract: In an embodiment, a server receives-a digital key request for a digital key to unlock a smart lock. A biometric feature request for collecting a biometric feature from the mobile device is generated and sent to the mobile device. A biometric feature corresponding to the biometric feature request is received. Identity information and a device identifier of the smart lock is received from another server. Based on the identity information, a matching biometric feature stored in a biometric feature database is determined. An identity of a user corresponding to the received biometric feature is verified based on the matching biometric feature. After the identity of the user is verified, smart lock information is identified. A digital key for unlocking the smart lock is generated based on the digital key request and the smart lock information and sent to the mobile device.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: September 7, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Hui Liao, Qi Huang, Shengbo Zhao
  • Publication number: 20210266171
    Abstract: Embodiments of this specification provide methods and systems for operating an IoT device An exemplary method comprises: receiving, by a user equipment, an operation instruction for the IoT device from a user, wherein the user equipment is communicatively coupled with the IoT device; identifying, by the user equipment, a biometric feature of the user; verifying, by the user equipment, an identity of the user based on the biometric feature; signing, by the user equipment, the operation instruction using a first user key of the user in response to the identity of the user being verified; transmitting, by the user equipment, the signed operation instruction to the IoT device; verifying, by the IoT device, the signed operation instruction using a second user key of the user; and executing, by the IoT device, the operation instruction in response to the signed operation instruction being verified.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 26, 2021
    Inventors: Qi HUANG, Hui LIAO
  • Patent number: 11094714
    Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming an array wafer comprises forming an alternating dielectric etch stop structure on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through contact in the periphery region and in contact with the alternating dielectric etch stop structure. The method further comprises forming a CMOS wafer and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the alternating dielectric etch stop structure, and in contact with the at least one first vertical through contact.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 17, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Liang Chen, Lei Xue, Wei Liu, Shi Qi Huang
  • Publication number: 20210197190
    Abstract: A planar volumetric device for quantifying and handling a body fluid sample is provided. The device has a planar main body, a body fluid sample flow path, an air pump and an air passage. The planar main body includes a first planar surface and a second planar surface. The body fluid sample flow path is disposed in the main body, and has a body fluid sample inlet, a middle junction and a body fluid sample outlet, wherein the middle junction and the body fluid sample outlet define therebetween a specific path segment, by which it is possible to externally observe to which extent the body fluid sample has filled up with the path segment. The air pump is configured to provide an operating air pressure. The air passage has a first end and a second end, wherein the first and the second ends are connected to the air pump and the middle junction respectively, and the specific path segment has a constant volume.
    Type: Application
    Filed: August 11, 2020
    Publication date: July 1, 2021
    Applicant: TAI-SAW Technology Co., Ltd.
    Inventors: Yi-Qi Huang, Wei-Yi Hsu, Pei-Tzu Hung, Szu-Heng Liu, Yu-Tung Huang
  • Publication number: 20210196166
    Abstract: A method for collecting a body fluid sample of a person to be examined is provided. The method comprises steps of: providing a body fluid sample collecting device and a body fluid sample inspection device for collecting the body fluid sample according to a test sampling requirement, wherein the body fluid sample collecting device includes a body fluid sample collecting region having an open hydrophilic layer with a specific layer area, and configured for collecting a predetermined amount of the body fluid sample; from a body surface of the person to be examined, causing the body fluid sample to be collected onto the body fluid sample collecting region until the body fluid sample covers the hydrophilic layer completely; and receiving the body fluid sample from the body fluid collecting region to be inspected in the body fluid sample inspection device.
    Type: Application
    Filed: August 11, 2020
    Publication date: July 1, 2021
    Applicant: TAI-SAW Technology Co., Ltd.
    Inventors: Wei-Yi Hsu, Pei-Tzu Hung, Yi-Qi Huang, Szu-Heng Liu, Yu-Tung Huang
  • Publication number: 20210203316
    Abstract: Devices for generating a delay output signal are disclosed. A device may include a first delay circuit and a second delay circuit coupled in series between a first node and a second node in a delay path for the device, and having a third node therebetween. The device may also include a third circuit coupled to the third node and configured to charge the third node responsive to detecting a signal has passed through the first node and the third node. Associated semiconductor devices and methods are also disclosed.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Hiroshi Akamatsu, Zhi Qi Huang
  • Publication number: 20210199898
    Abstract: An optical fiber connector is provided. The optical fiber connector comprises a plastic housing. The optical fiber connector comprises a metallic clip. The plastic housing is adapted to connect the optical fiber connector to an optical fiber adapter. The metallic clip is arranged at a side of the plastic housing. The metallic clip extends from the plastic housing. The metallic clip is adapted to press against a metallic part of the optical fiber adapter.
    Type: Application
    Filed: March 13, 2018
    Publication date: July 1, 2021
    Inventors: Juntao Deng, Bolin Jiang, Qi Huang, Marcus Bloom-Pflug
  • Patent number: 11049834
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. The second semiconductor structure further includes a second bonding layer including second bonding contacts. At least one second bonding contact is in contact with a respective second interconnect. At least another second bonding contact is separated from the second interconnects. The semiconductor device further includes a bonding interface between the first and second bonding layers.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: June 29, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
  • Publication number: 20210166762
    Abstract: Local word line driver device, memory device, and fabrication method are provided. A local word line driver device includes a substrate and an array of transistor structures formed on the substrate. The transistor structures are configured in rows and columns. The substrate includes a plurality of first field regions each between adjacent rows of the transistor structures, and a plurality of second field regions each between adjacent columns of the transistor structures. A deep trench isolation structure is formed in at least one field region of: the plurality of first field regions or the plurality of second field regions, of the substrate.
    Type: Application
    Filed: June 1, 2020
    Publication date: June 3, 2021
    Inventors: Cheng GAN, Wei LIU, Shi Qi HUANG, Shunfu CHEN
  • Patent number: 11022766
    Abstract: We generally describe an optical transceiver connector (100) comprising: a first portion (102) comprising a first port (101) configured to releasably receive an optical connector (202); and a second portion (104) comprising a second port (103) configured to releasably receive an optical converter element (205), wherein an opening of the first port (101) faces towards a first direction opposite to a second direction towards which an opening of the second port (103) faces, and wherein the first port (101) is aligned with the second port (103) for establishing a releasable, light-coupling-capable connection between a said optical connector (202) to be received by the first port (101) and a said optical converter element (205) to be received by the second port (103).
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: June 1, 2021
    Assignee: Leoni Kabel GMBH
    Inventors: Bolin Jiang, Juntao Deng, Marcus Bloom-Pflug, Qi Huang
  • Patent number: 10998893
    Abstract: Methods and apparatus for generating a delayed output signal from an input signal applied to an RC delay circuit of a semiconductor device during an active mode. The RC delay circuit is configured to pull up a voltage level on a node responsive to a reset signal during a stand-by mode.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Akamatsu, Zhi Qi Huang
  • Patent number: 10992481
    Abstract: A computer-implemented method includes receiving, by an electronic device, a two-dimensional code generation request from a user operating the electronic device, the electronic device comprising secure element; obtaining, by the electronic device, two-dimensional code generation data, wherein the two-dimensional code generation data comprises account data of the user and timestamp data of the electronic device; obtaining, by the electronic device, signature data based on a predetermined signature algorithm stored in the secure element; and generating, by the electronic device, a target two-dimensional code based on the two-dimensional code generation data and the signature data.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 27, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Qi Huang, Shengbo Zhao, Hui Liao, Zhiwei Wang, Yawen Wei
  • Publication number: 20210094593
    Abstract: A startup stage protection device used in Electric Multiple Unit (EMU) train coupler experiment is provided between two test cars. The startup stage protection device is arranged between and tightly abuts two test cars at the starting stage of the experiment to receive a compressing force in place of the coupler. The startup stage protection device separates from the two test cars after the end of the starting stage.
    Type: Application
    Filed: May 30, 2019
    Publication date: April 1, 2021
    Applicant: CENTRAL SOUTH UNIVERSITY
    Inventors: Ping XU, Shuguang YAO, Bowen TAN, Yong PENG, Zhaijun LU, Chengming SUN, Kai XU, Qi HUANG
  • Publication number: 20210048557
    Abstract: The present disclosure relates to a method and a device for simulating discharge, and a computer device. The method includes steps of: acquiring forcing data; simulating the discharge of a river basin to be measured according to the forcing data and a calibrated hydrological model of the river basin, to obtain a simulated discharge of the river basin; the calibrated hydrological model is a hydrological model including calibrated model parameters; the calibrated model parameters are obtained by calibrating model parameters of an initial hydrological model, according to a converted discharge of the river basin to be measured and the GRACE-derived total water storage changes of the river basin to be measured.
    Type: Application
    Filed: November 17, 2019
    Publication date: February 18, 2021
    Applicant: Tsinghua University
    Inventors: DI LONG, QI HUANG
  • Publication number: 20210051024
    Abstract: A computer-implemented method includes receiving, by an electronic device, a two-dimensional code generation request from a user operating the electronic device, the electronic device comprising secure element; obtaining, by the electronic device, two-dimensional code generation data, wherein the two-dimensional code generation data comprises account data of the user and timestamp data of the electronic device; obtaining, by the electronic device, signature data based on a predetermined signature algorithm stored in the secure element; and generating, by the electronic device, a target two-dimensional code based on the two-dimensional code generation data and the signature data.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Applicant: Advanced New Technologies Co., Ltd.
    Inventors: Qi Huang, Shengbo Zhao, Hui Liao, Zhiwei Wang, Yawen Wei
  • Publication number: 20210043019
    Abstract: Embodiments of the present specification disclose unlocking methods of smart locks.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Applicant: Advanced New Technologies Co., Ltd.
    Inventors: Hui Liao, Qi Huang, Shengbo Zhao
  • Publication number: 20210035941
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first interconnect layer including first interconnects is formed above a first substrate. A first bonding layer including first bonding contacts is formed above the first interconnect layer, such that each first interconnect is in contact with a respective first bonding contact. A second interconnect layer including second interconnects is formed above a second substrate. A second bonding layer including second bonding contacts is formed above the second interconnect layer, such that at least one second bonding contact is in contact with a respective second interconnect, and at least another second bonding contact is separated from the second interconnects. The first and second substrates are bonded in a face-to-face manner, such that each first bonding contact is in contact with one second bonding contact at a bonding interface.
    Type: Application
    Filed: October 6, 2020
    Publication date: February 4, 2021
    Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
  • Publication number: 20210035887
    Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.
    Type: Application
    Filed: December 30, 2019
    Publication date: February 4, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Liang CHEN, Lei XUE, Wei LIU, Shi Qi HUANG