Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: Sensor-integrated prosthetic valves that can comprise a variety of features, including a plurality of valve leaflets, a frame assembly configured to support the plurality of valve leaflets and define a plurality of commissure supports terminating at an outflow end of the prosthetic valve, a sensor device associated with the frame assembly and configured to generate a sensor signal, for example, a sensor signal indicating deflection of one or more of the plurality of commissure supports, and a transmitter assembly configured to receive the sensor signal from the sensor device and wirelessly transmit a transmission signal that is based at least in part on the sensor signal.

Abstract: Single loop inductive sensors are widely deployed in infrastructure for traffic data collection, however, these loops currently provide little more than vehicle detection. A system and method are provided that enable single loop inductive sensors to be used for vehicle classification (e.g., identification as motorcycle, passenger car, bus, etc.). Classification may be done using the Federal Highway Administration's 13 class system. Initially a signature library is built from vehicle signatures with known classifications. Vehicle signature waveforms of unknown classification obtained from inductive loop sensors are analyzed to identify specific features in the waveform including the number of “peaks”, the first peak location and its magnitude. A classifier (e.g., K-nearest neighbor) uses a representation of the vehicle signature and the features to determine from the signature library the classification of the vehicle.

Abstract: An operating method for improving the performance of a selector device is provided, including: determining and applying a direct current (DC) or alternating current (AC) operating voltage and a limit current of the selector device, so that the selector device circulates until a off-state resistance is reduced; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is reduced to a minimum value; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is increased; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is increased to a maximum value; and adjusting the operating voltage and the limit current, and performing DC or AC operation pulsed operation on a selector.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract: An operating method for improving the performance of a selector device is provided, including: determining and applying a direct current (DC) or alternating current (AC) operating voltage and a limit current of the selector device, so that the selector device circulates until a off-state resistance is reduced; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is reduced to a minimum value; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is increased; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is increased to a maximum value; and adjusting the operating voltage and the limit current, and performing DC or AC operation pulsed operation on a selector.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: An integrated circuit device having a plurality of stacked dies is described. The integrated circuit device comprises a first die of the plurality of stacked dies having an input/output element configured to receive an input signal, the first die comprising a signal driver circuit configured to provide the input signal to each die of the plurality of stacked dies and a chip select circuit for generating a plurality of chip select signals for the plurality of stacked dies; and a second die of the plurality of stacked dies coupled to the first die, the second die having a function block configured to the receive the input signal; wherein the second die receives the input signal in response to a chip select signal of the plurality of chip select signals that corresponds to the second die. A method of implementing an integrated circuit device having a plurality of stacked dies is also described.