Abstract: A system, method, and computer program product are provided for merging two or more supply rails into a merged supply rail. The method comprises receiving two or more current measurement signals associated with two or more supply rails, selecting one supply rail from the two or more supply rails, based on the current measurement signals, and enabling the selected supply rail to source current into a merged supply rail.

Abstract: Embodiments of the present invention disclose a method for switching of a device, an M2M platform and a network system. The method includes: a machine-to-machine M2M platform receives a re-registration message including a position of a device in a network service capability layer NSCL resource tree before registration and a position of the device in the resource tree of the NSCL after registration; the M2M platform generates mapping relationship between the position of the device in the resource tree of the NSCL before registration and the position of the device in the resource tree of the NSCL after registration. By way of the present invention, the problem in the prior art can be solved in a manner of re-registration.

Abstract: A power subsystem is configured to manage the maximum power usage of a computer subsystem. A power detector determines when power usage approaches the maximum capability of the power supply. The power detector generates a signal that corresponds to power usage. A controller then applies the signal to the system voltage regulator as a secondary regulation function such that the output voltage is reduced in a manner that supports maximum operating voltage while limiting power usage to within the capability of the power supply. The controller may configure the signal to implement the secondary regulation function as a modification of the feedback voltage, the reference voltage, or the current feedback of the regulator. As a result the subsystem causes the computer subsystem to operate at an optimum point on the voltage-current curve of the power supply.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract: A dynamic multiple input rail switching unit includes a plurality of DC input voltage rails and a rail switching section coupled to the plurality of DC input voltage rails that is configured to individually connect selected ones of the plurality of DC input voltage rails to a switched rail output. The dynamic multiple input rail switching unit also includes a rail selection section that is coupled to the rail switching section and configured to dynamically choose the selected ones by balancing rail supply currents from the plurality of DC input voltage rails based on rail supply current capacity margins and a switched rail output current. A dynamic multiple input rail switching unit operating method, and a dynamic multiple input rail power converter are also provided.

Abstract: A seamless connecting drain structure of a metallic sink is provided. When the metallic sink is installed, a drain pipe or a drain connector as a drain end of a water outlet of the metallic sink is connected with an annular ring of the water outlet through a screw sleeve with inner threads to mesh with outer threads of a connecting sleeve, or a drain connector having inner threads is directly screwed to the outer threads of the connecting sleeve to connect with the annular ring. The entire structure of the water outlet is convenient for the drain pipe or the drain connector to be connected with the annular ring. Through the annular ring, the bottom of the metallic sink extends outward to form a complete configuration, so that the drain end of the water outlet and the drain pipe or the drain connector are connected seamlessly.

Abstract: A seamless locking drain connector structure of a metallic sink is provided. A water outlet of a bottom of the metallic sink is integrally formed with an annular ring extending outward from the bottom of the metallic sink. The annular ring is fixedly connected with a connecting sleeve. The connecting sleeve is formed with outer threads. An open end of a stepped trough of the drain connector is formed with a retaining rim portion relative to the bottom end of the connecting sleeve. The retaining rim portion is connected with a locking sleeve. The locking sleeve is formed with inner threads corresponding to the outer threads of the connecting sleeve. The inner threads mesh with the outer threads, such that the retaining rim portion of the drain connector is tightly locked to the bottom end of the connecting sleeve to connect with the annular ring and the water outlet.

Abstract: System and method of controlling an object via control device having integrated touch and displacement control. An embodiment includes an input device having a control stick with an integrated touch sensor, where the control stick may be displaced to provide control of a first functionality of an object, and a user touch sensed by the integrated touch sensor provides control of a second functionality of the object. Additionally, a method is described for controlling an object using a control device integrating displacement and touch control modes. A motion of the object may be controlled, such that inputs from the control device control a relative movement, an absolute movement, and/or a combination of relative and absolute movement for the object. An embodiment includes a game controller having a control device according to the present disclosure.

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract: An electronic device includes a base, and a lighting apparatus mounted to the base. The lighting apparatus includes a bracket mounted to the base, a pivoting member pivotably attached to the bracket, and a lighting unit fixed in the pivoting member. The pivoting member is pivoted out of the bracket to expose and turn on the lighting unit. The pivoting member is pivoted into the bracket to cover and turn off the lighting unit.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: An inverter includes: a PMOS comprising: a p-type source region, a p-type drain region, a p-channel region between the p-type source region and the p-type drain region, and a PMOS metal gate region; a NMOS, comprising: an n-type source region, an n-type drain region, an n-channel region between the n-type source region and the n-type drain region, and a NMOS metal gate region; an insulating layer above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact between the NMOS metal gate region and the PMOS metal gate region.

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract: Embodiments of the present invention provide a machine-to-machine communications privacy protection method and system, a machine-to-machine communications service management entity, and a related device. The method includes: after receiving a location access message, determining, by a service management entity and according to locating information, an entity that performs privacy inspection; and triggering, by the service management entity, the entity that performs privacy inspection to perform privacy inspection. The M2M service management entity determines in advance the entity that performs privacy inspection and triggers the entity that performs privacy inspection to perform privacy inspection. Therefore, with the method provided in the present invention, message interaction on an mId interface is reduced, thereby reducing a message overhead.

Abstract: A dynamic multiple input rail switching unit includes a plurality of DC input voltage rails and a rail switching section coupled to the plurality of DC input voltage rails that is configured to individually connect selected ones of the plurality of DC input voltage rails to a switched rail output. The dynamic multiple input rail switching unit also includes a rail selection section that is coupled to the rail switching section and configured to dynamically choose the selected ones by balancing rail supply currents from the plurality of DC input voltage rails based on rail supply current capacity margins and a switched rail output current. A dynamic multiple input rail switching unit operating method, and a dynamic multiple input rail power converter are also provided.