Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

Abstract: Embodiments of the present invention provide a machine-to-machine communications privacy protection method and system, a machine-to-machine communications service management entity, and a related device. The method includes: after receiving a location access message, determining, by a service management entity and according to locating information, an entity that performs privacy inspection; and triggering, by the service management entity, the entity that performs privacy inspection to perform privacy inspection. The M2M service management entity determines in advance the entity that performs privacy inspection and triggers the entity that performs privacy inspection to perform privacy inspection. Therefore, with the method provided in the present invention, message interaction on an mId interface is reduced, thereby reducing a message overhead.

Abstract: A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.

Abstract: An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.

Abstract: A display includes an outer frame defining an circumferential opening in a center, a protective glass accommodated in the opening, an inner frame mounted to the outer frame below the glass, and a liquid crystal display panel mounted to the inner frame. The inner side of the outer frame bounding the opening defines a latching slot to receive sides of the protective glass. The protective glass protects the liquid crystal display panel from being scraped or scratched.

Abstract: A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

Abstract: A sine-wave current line-start three-phase rare-earth permanent magnet synchronous motor includes a motor shaft, a rotor and a stator. The rotor is disposed inside the stator and rotates around the motor shaft. The rotor includes P pairs of poles. Each pole includes a polar arched surface. A planar surface is formed between adjacent polar arched surfaces. Thus, a non-uniform air gap is formed between the pole face of the rotor and the inner circumferential surface of the stator. By the use of a salient-pole structure with the non-uniform air gap, the asymmetry of the magnetic circuit caused by permanent magnets can be offset, thereby making the manufacturing process of the rotor simplified, the negative sequence components of the rotor current during the line starting process reduced significantly, the starting performance improved, the sine-wave current provided during the operating process, the harmonic loss reduced, and the motor efficiency enhanced.

Abstract: A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

Abstract: A display includes an outer frame defining an circumferential opening in a center, a protective glass accommodated in the opening, an inner frame mounted to the outer frame below the glass, and a liquid crystal display panel mounted to the inner frame. The inner side of the outer frame bounding the opening defines a latching slot to receive sides of the protective glass. The protective glass protects the liquid crystal display panel from being scraped or scratched.