Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.

Abstract: An electrical contact (20) for using in a CPU (central processing unit) socket, includes a planar base portion (201), a pair of flexible arms (203) extending from the planar base portion, a pair of contact portions (204) being orthogonal to the flexible arms, a pair of stopper portions (205) coplanarly formed on the flexible arms and a solder portion (206) being orthogonal to the planar base portion and extending parallel to the contact portions.

Abstract: A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,—the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

Abstract: The invention provides for a formulation for coating one or more microprojections which reduces or minimizes the loss of counterions from the coating in order to achieve a pH-stabilized formulation.

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract: An integrated circuit device is described. In particular, the integrated circuit comprises a substrate comprising active devices; a plurality of metal layers formed over the substrate, the plurality of metal layers being separated by insulating layers; a plurality of vias enabling connections to the active devices of the substrate; a contact pad support structure defining an opening in a metal layer of the plurality of metal layers and being coupled to an interconnect line; and a contact pad formed over the contact pad support structure. A method of implementing a contact pad in an integrated circuit is also disclosed.

Abstract: An electrical contact (20) for using in a CPU (central processing unit) socket, includes a planar base portion (201), a pair of flexible arms (203) extending from the planar base portion, a pair of contact portions (204) being orthogonal to the flexible arms, a pair of stopper portions (205) coplanarly formed on the flexible arms and a solder portion (206) being orthogonal to the planar base portion and extending parallel to the contact portions.

Abstract: Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: This invention relates to a method for inhibiting a decrease in the transdermal flux of an agent that is being transdermally delivered or sampled over a prolonged period of time wherein the delivery or sampling involves disrupting at least the stratum corneum layer of the skin to form pathways through which the agent passes. The desired result is achieved by co-delivering or co-sampling the agent with an amount of at least one anti-healing agent wherein the amount of the anti-healing agent is effective in inhibiting a decrease in the agent transdermal flux compared to when the delivery or sampling of the agent is done under substantially identical conditions except in the absence of the anti-healing agent(s).

Abstract: A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second poly layer. This configuration allows for an area-efficient layout that is easily shrinkable as compared to prior art memory cells. In addition, stacking the control and floating gates results in higher capacitive coupling. The EEPROM cell also includes an access gate, a tunnel capacitor, and at least one inverter. In some embodiments, the EEPROM cell can be advantageously used to configure programmable logic without need for a conloading step.

Abstract: A device (12) and method are provided for percutaneous transdermal delivery of a potent pharmacologically active agent. The agent is dissolved in water to form an aqueous coating solution having an appropriate viscosity for coating extremely tiny skin piercing elements (10). The coating solution is applied to the skin piercing elements (10) using known coating techniques and then dried. The device (12) is applied to the skin of a living animal (e.g., a human), causing the microprotrusions (10) to pierce the stratum corneum and deliver a therapeutically effect dose of the agent to the animal.

Abstract: A device and method for enhancing skin piercing by microprotrusions involves pre-stretching the skin to enhance pathway formation when the microprotrusions are pressed into the skin. An expandable device includes skin engaging opposite ends that contact the skin surface so that when the device is expanded the skin is stretched. The skin is placed under a tension of about 0.01 to about 10 megapascals, preferably about 0.05 to 2 megapascals. The device has a plurality of microprotrusions which penetrate the skin while the skin is being stretched by the expanded device. Another stretching device employs suction for skin stretching.

Abstract: A device and method for enhancing skin piercing by microprotrusions involves pre-stretching the skin to enhance pathway formation when the microprotrusions are pressed into the skin. An expandable device includes skin engaging opposite ends that contact the skin surface so that when the device is expanded the skin is stretched. The skin is placed under a tension of about 0.01 to about 10 megapascals, preferably about 0.05 to 2 megapascals. The device has a plurality of microprotrusions which penetrate the skin while the skin is being stretched by the expanded device. Another stretching device employs suction for skin stretching.

Abstract: A hot swap circuit board and associated cable and connector arrangement for an ATA100 computer-disk drive interface is disclosed. The hot swap circuit board comprises a key-switched power supply control circuit with a simultaneously key-operated mechanical lock, a logic control circuit for READ and WRITE control signals and a set of logic switchable bi-directional impedance circuits with signal regeneration for the control and data signals across the ATA100 Interface. During normal operation, a security lock on the hot swap circuit board is kept in its locked position thus preventing any accidental disconnection of the ATA100 interface connector while simultaneously supplying electrical power and transmitted and regenerated control and data signals across the ATA100 interface. The unlocking mechanism is also disclosed.

Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage.

Abstract: A hot swap circuit board and associated cable and connector arrangement for an ATA100 computer-disk drive interface is disclosed. The hot swap circuit board comprises a key-switched power supply control circuit with a simultaneously key-operated mechanical lock, a logic control circuit for READ and WRITE control signals and a set of logic switchable bi-directional impedance circuits with signal regeneration for the control and data signals across the ATA100 Interface. During normal operation, a security lock on the hot swap circuit board is kept in its locked position thus preventing any accidental disconnection of the ATA100 interface connector while simultaneously supplying electrical power and transmitted and regenerated control and data signals across the ATA100 interface. The unlocking mechanism is also disclosed.