Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N?1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit and a voltage control circuit; the driving signal generation circuit generates an Nth stage of driving signal, the output control circuit connects the first control node and the second node under the control of the potential of the first node; the gating circuit controls to write a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to a potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the third control node.

Abstract: A display substrate and a display device. In the display substrate, a plurality of first output ends of the plurality of straight edge gate driving structures are connected to the plurality of first signal lines through a plurality of first connection structures, and a plurality of second output ends of the plurality of rounded corner gate driving structures are connected to the plurality of second signal lines through a plurality of second connection structures; the first conductive part and the second conductive part are located in a same conductive layer, and a number and a type of the plurality of via connection structures in each of the plurality of first connection structures are the same as a number and a type of the plurality of via connection structures in each of the plurality of second connection structures.

Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N?1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.

Abstract: The present disclosure generally relates to high-performance flexible thermoelectric generators (f-TEGs) for heat concentration and dissipation. In some embodiments, the f-TEGs can be incorporated into wearable devices. The f-TEG device can include an f-TEG network of thermoelectric units that include multifunctional thin copper disks that can be used as electrodes, heat concentrators and spreaders, spacers, and flexibility enablers. Each electrode can include a spacer extending therefrom to suppress the heat loss between the hot and the cold sides through conduction and convection across a thermoelectric pillar disposed therebetween. In some embodiments, the f-TEG network can be associated with a fabric to provide good wearability and comfort even in wet thermal environments.

Abstract: An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

Abstract: Methods and apparatus are provided for encoding and decoding binary sets using adaptive tree selection. In one exemplary encoding method embodiment, picture data is encoded for a block in a picture; in which one of a plurality of trees structures is selected to code a binary set of data for indicating coefficient significance for the block. In another exemplary encoding method embodiment, picture data is encoded for a block in a picture, in which one or more trees are used to encode a binary set of data for indicating significance for the block, the one or more trees each having a plurality of nodes, at least one of the nodes of the one or more trees being modified responsive to at least one parameter.

Abstract: Methods and apparatus are provided for improved chroma encoding and decoding. An apparatus includes an encoder (400) for encoding picture data for at least a block in a picture. Multiple partition types are supported for intra chroma coding of the block. The multiple partition types include a set of chroma partition types and a set of luma partition types. The set of chroma partition types are different than the set of luma partition types.

Abstract: Methods and apparatus are provided for signaling intra prediction for large blocks for video encoders and decoders. An apparatus includes a video encoder for encoding picture data for at least one large block in a picture by signaling intra prediction for the at least one large block. The intra prediction is signaled by selecting a basic coding unit size and assigning a single spatial intra partition type for the basic coding unit size. The single spatial intra partition type is selectable from among a plurality of spatial intra partition types. The at least one large block has a large block size greater than a basic coding unit size. The intra prediction may be performed for the at least one large block by at least one of splitting from the large block size to the basic coding unit size.

Abstract: A display substrate, a display device, a high-precision metal mask are provided. The display substrate includes first, second, third sub-pixels. In first direction, first and third sub-pixels are alternated to form first sub-pixel rows, second sub-pixels form second sub-pixel rows. In second direction, first and second sub-pixel rows are alternated, first direction is approximately perpendicular to second direction. Two first and two third sub-pixels in two adjacent rows and two adjacent columns form a 2*2 array, in the array, two first sub-pixels are in different rows and different columns, two third sub-pixels are in different rows and different columns, at least one of two first and two third sub-pixels is a pattern where corner is cut off, connection lines of centers of two first and two third sub-pixels form non-square virtual quadrilateral, and second sub-pixel is within virtual quadrilateral.

Abstract: An induction-type panel lamp and a lighting system are provided. The induction-type panel lamp includes a fixing frame, a light source component, and a sensing element, wherein the fixing frame is provided with a through space, an accommodating groove, and a second guide hole, the second guide hole communicates with the accommodating groove, the light source component is accommodated in the through space, the sensing element includes a detecting portion and a conducting portion which are connected to each other, the conducting portion penetrates the second guide hole and extends into the accommodating groove, the conducting portion is electrically connected to the light source component, and the detecting portion is arranged outside the fixing frame.

Abstract: Provided are fixing clamp and turn-off device. The fixing clamp includes clamp body and an elastic plate, wherein the clamp body includes first section, second section, and third section, the first section and the third section are separately connected to two ends of the second section, and the first section and the third section both are located at the same side of the second section; the elastic plate includes connecting end and an open end, the connecting end is connected to the first section, and gap is provided between the open end and the third section, so that the elastic plate is in cantilevered structure relative to the first section; and an accommodation space is formed between the clamp body and the elastic plate, and at least one of the first section, the second section, and the third section is provided with protrusion part.

Abstract: A mask sheet for evaporation on a substrate is provided, and the mask sheet includes: a plurality of first ribs extending in a first direction; and a plurality of second ribs extending in a second direction intersecting the first direction, the mask sheet includes a first region for an evaporation of a first exposure region of the substrate and a second region for an evaporation of a second exposure region of the substrate, a third rib is provided at a boundary of the first region and the second region so as to shield an overlapping exposure region between the first exposure region and the second exposure region, the third rib includes a first sub-rib, a second sub-rib, and a spacer for separating the first sub-rib and the second sub-rib, and the third rib has a width greater than that of the first rib.

Abstract: A block of a video frame can be encoded using inter-prediction, and the motion vector of the block can be encoded based on a motion vector reference of a merge candidate. Some video codecs allow a large range of temporal and spatial neighbors to be considered as potential merge candidates. It is not practical to perform motion compensation and rate-distortion optimization for all possible merge candidates. To address this concern, a hardware-efficient process can be implemented to rank and select merge candidates. A reference frame priority list is applied to select a subset of potential reference frame combinations. An efficient top-K sorting algorithm is applied to identify merge candidates for each reference frame combination and keep top merge candidates with highest weights. Motion compensation and rate-distortion optimization are performed on the top merge candidates only.