Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

Abstract: A mask includes a frame, at least one mask sheet, and a shielding plate. The frame includes a plurality of borders. The borders are connected end to end in sequence to form the frame with a first hollow region. A mask sheet includes a pattern region and non-pattern regions. The pattern region includes at least one evaporation hole. The shielding plate includes a plurality of shielding strips. The plurality of shielding strips are arranged crosswise to form a plurality of second hollow regions. Orthogonal projections of the second hollow regions on a plane perpendicular to a thickness direction of the frame are located within a range of an orthogonal projection of the first hollow region on the plane. An inner edge of an orthogonal projection of the frame on the plane is located within a range of an orthogonal projection of the shielding plate on the plane.

Abstract: Methods and apparatus are provided for encoding and decoding binary sets using adaptive tree selection. In one exemplary encoding method embodiment, picture data is encoded for a block in a picture; in which one of a plurality of trees structures is selected to code a binary set of data for indicating coefficient significance for the block. In another exemplary encoding method embodiment, picture data is encoded for a block in a picture, in which one or more trees are used to encode a binary set of data for indicating coefficient significance for the block, the one or more trees each having a plurality of nodes, at least one of the nodes of the one or more trees being modified responsive to at least one parameter.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.

Abstract: A power tool includes an electric motor assembly disposed at least partially in a housing and including a first electric motor, a second electric motor, and a connector, where limit values of efficiency of the electric motor assembly constitute a total efficiency interval, and efficiency values of the electric motor assembly greater than or equal to 70% constitute a first efficiency interval, where the ratio of the first efficiency interval to the total efficiency interval is greater than or equal to 0.5.

Abstract: A pixel array includes a plurality of sub-pixels, which include first to third sub-pixels. The first and third sub-pixels are alternately arranged along a row direction and form first pixel rows. The first and third sub-pixels, which are in a same column, in the first pixel rows are alternately arranged, and the second sub-pixels are arranged side by side along the row direction and form second pixel rows. Lines sequentially connecting centers of two of the first sub-pixels and two of the third sub-pixels, which are arranged in an array, together form a first virtual quadrilateral, and one of the second sub-pixels is in each first virtual quadrilateral. A straight line in the row direction or in a column direction, which passes through a center of each sub-pixel of at least one of the plurality of sub-pixels, divides the sub-pixel into two parts having areas different from each other.

Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N?1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit and a voltage control circuit; the driving signal generation circuit generates an Nth stage of driving signal, the output control circuit connects the first control node and the second node under the control of the potential of the first node; the gating circuit controls to write a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to a potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the third control node.

Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N?1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.

Abstract: A display substrate and a display device. In the display substrate, a plurality of first output ends of the plurality of straight edge gate driving structures are connected to the plurality of first signal lines through a plurality of first connection structures, and a plurality of second output ends of the plurality of rounded corner gate driving structures are connected to the plurality of second signal lines through a plurality of second connection structures; the first conductive part and the second conductive part are located in a same conductive layer, and a number and a type of the plurality of via connection structures in each of the plurality of first connection structures are the same as a number and a type of the plurality of via connection structures in each of the plurality of second connection structures.

Abstract: The present disclosure generally relates to high-performance flexible thermoelectric generators (f-TEGs) for heat concentration and dissipation. In some embodiments, the f-TEGs can be incorporated into wearable devices. The f-TEG device can include an f-TEG network of thermoelectric units that include multifunctional thin copper disks that can be used as electrodes, heat concentrators and spreaders, spacers, and flexibility enablers. Each electrode can include a spacer extending therefrom to suppress the heat loss between the hot and the cold sides through conduction and convection across a thermoelectric pillar disposed therebetween. In some embodiments, the f-TEG network can be associated with a fabric to provide good wearability and comfort even in wet thermal environments.

Abstract: An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

Abstract: Methods and apparatus are provided for encoding and decoding binary sets using adaptive tree selection. In one exemplary encoding method embodiment, picture data is encoded for a block in a picture; in which one of a plurality of trees structures is selected to code a binary set of data for indicating coefficient significance for the block. In another exemplary encoding method embodiment, picture data is encoded for a block in a picture, in which one or more trees are used to encode a binary set of data for indicating significance for the block, the one or more trees each having a plurality of nodes, at least one of the nodes of the one or more trees being modified responsive to at least one parameter.

Abstract: Methods and apparatus are provided for improved chroma encoding and decoding. An apparatus includes an encoder (400) for encoding picture data for at least a block in a picture. Multiple partition types are supported for intra chroma coding of the block. The multiple partition types include a set of chroma partition types and a set of luma partition types. The set of chroma partition types are different than the set of luma partition types.