Abstract: The present disclosure provides an assay cartridge used in a PCR-based molecular diagnostic device. In one embodiment, the assay cartridge comprises (1) an elongated body having a proximal end, a distal end and a plurality of compartments arranged between the proximal end and the distal end, said plurality of compartments include at least a first pipette tip holder near the proximal end, and a second pipette tip holder near the distal end; and (2) a seal assembly covering the elongated body comprising a rigid frame which matches the top periphery of the elongated body, and an elastic top mounted on the rigid frame, the elastic top comprising a first sub-portion near the proximal end comprising a first ring structure that matches the first pipette holder, and a second sub-portion near the distal end comprising a second ring structure that matches the second pipette holder.

Abstract: Provided are a support apparatus and a flexible device. The support apparatus comprises a support substrate, an electromagnetic support cavity array which is located on the support substrate and includes a plurality of electromagnetic support cavities, a plurality of magnetic field generation circuits, and a control module, where the magnetic field generation circuits are electrically connected to the control module, and the control module is configured to control the plurality of magnetic field generation circuits to generate magnetic fields to make the electromagnetic support cavities deform along a direction perpendicular to a plane in which the support substrate is located. Through the scheme, the electromagnetic support cavity array is provided on the support substrate, and the magnetic field generation circuits are controlled by the control module to generate magnetic fields.

Abstract: A display substrate, a display device, a high-precision metal mask are provided. The display substrate includes first, second, third sub-pixels. In first direction, first and third sub-pixels are alternant to form first sub-pixel rows, second sub-pixels form second sub-pixel rows. In second direction, first and second sub-pixel rows are alternant, first direction is approximately perpendicular to second direction. Two first and two third sub-pixels in two adjacent rows and two adjacent columns form a 2*2 array, in the array, two first sub-pixels are in different rows and different columns, two third sub-pixels are in different rows and different columns, at least one of two first and two third sub-pixels is a pattern where corner is cut off, connection lines of centers of two first and two third sub-pixels form non-square virtual quadrilateral, and second sub-pixel is within virtual quadrilateral. The display effect can be improved.

Abstract: A composite item of footwear and handwear having a main body to accommodate the hand/foot of a wearer of the item, the main body comprising an outer layer, an inner layer and a waterproof and breathable intermediate layer between the outer and inner layers, and an opening through which a foot/hand can be inserted, the opening defined by a cuff arrangement comprising a cuff region that comprises an end region of each of the inner and intermediate layers and a cuff inner portion of the outer layer that extends beyond the said end regions, the cuff arrangement further comprising a waterproof cuff band fixed to one or both of the cuff inner portion and end region of the inner layer to lie over and be fixed to the outside of the outer layer, the location at which the waterproof cuff band is fixed to the outer layer is at a distance from the opening that is greater than the distance between the opening and the location at which the waterproof cuff band is fixed to the cuff inner portion or end region of the inner l

Abstract: The embodiments provide a detection circuit and a detection method. The detection circuit includes an ESD protection device, a first fuse and a transistor. A first terminal of the ESD protection device is connected to a first terminal of the first fuse, and a connection terminal of the ESD protection device and the first fuse serves as a first test terminal; a second terminal of the first fuse is connected to a gate electrode of the transistor, and a connection terminal of the first fuse and the transistor serves as a second test terminal; and a second terminal of the ESD protection device is connected to at least one of a source electrode, drain electrode or substrate of the transistor, and a connection terminal of the ESD protection device and the transistor serves as a third test terminal.

Abstract: The present disclosure provides an electro-static discharge protection device for a semiconductor, including: a substrate of a first conductive type, a deep well region of a second conductive type being formed in the substrate of the first conductive type; first diodes, located in the deep well region of the second conductive type, anodes of the first diodes being connected to a first voltage through a plurality of first metal lines; second diodes, located in the deep well region of the second conductive type; a first pad, connected to the anodes of the first diodes through the plurality of first metal lines, and connected to the first voltage; a second pad, connected to cathodes of the second diodes through a plurality of second metal lines, and connected to a second voltage.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

Abstract: Methods and apparatus are provided for adaptive motion vector candidate ordering for video encoding and decoding. An apparatus includes a video encoder (100) for encoding a block in a picture by selecting an order of motion vector predictor candidates for the block responsive to a characteristic available at both the video encoder and a corresponding decoder. The characteristic excludes a mode in which the block is partitioned.

Abstract: The present disclosure relates to a latch-up test structure, including: a substrate of a first conductive type; a first well region of a second conductive type, located in the substrate of the first conductive type; a first doped region of the first conductive type, located in the first well region of the second conductive type; a first doped region of the second conductive type, located in the first well region of the second conductive type; and a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type.

Abstract: The present disclosure provides a latch-up test structure, including: a substrate of a first conductive type; a first well region of the first conductive type, located in the substrate of the first conductive type; a first doped region of the first conductive type, located in the first well region of the first conductive type; a first doped region of a second conductive type, located in the first well region of the first conductive type; and a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type.

Abstract: The present disclosure provides a diode-triggered bidirectional silicon controlled rectifier and circuit. The silicon controlled rectifier includes: a P-type substrate; a first P well formed in the P-type substrate, a first P-type doped region and a first N-type doped region being formed in the first P well; a second P well formed in the P-type substrate, a third N-type doped region and a fourth P-type doped region being formed in the second P well; and an N well formed in the P-type substrate, a second P-type doped region, a second N-type doped region and a third P-type doped region being formed in the N well. The second N-type doped region is electrically connected with a positive electrode of a diode string, and the first P-type doped region and the fourth P-type doped region are electrically connected with a negative electrode of the diode string.

Abstract: Methods and apparatus are provided for collaborative partition coding for region based filters. An apparatus includes a video encoder (100) for encoding image data for a plurality of regions in a picture. The video encoder (100) includes multiple filters for filtering the image data based on region partition information for the plurality of regions. The region partition information for the plurality of regions is shared between the multiple filters.

Abstract: An electro-static discharge protection circuit and a semiconductor device are provided. The electro-static discharge protection circuit includes: an electro-static discharge path including a Silicon Controlled Rectifier (SCR) connected between a first potential terminal and a second potential terminal; a Negative channel-Metal-Oxide-Semiconductor (NMOS) transistor connected to the SCR and configured to be turned on by an electro-static voltage, to trigger the SCR to be turned on; and a first resistance connected in parallel with at least part of the electro-static discharge path and configured to shunt a current of the electro-static discharge path when the SCR is turned on.

Abstract: The present disclosure provides an electrostatic discharge protection device, and relates to the technical field of semiconductors. A first P-type heavily-doped region and a first N-type heavily-doped region of the electrostatic discharge protection device are located in a P well, a second P-type heavily-doped region and a third N-type heavily-doped region are located in a first N well, one part of a second N-type heavily-doped region is located in the P well, the other part is located in the first N well, and the P well and the first N well are located in a P-type substrate. The P-type substrate is provided with a gate structure, the gate structure, the first N-type heavily-doped region, and the second N-type heavily-doped region form a transistor, the first N-type heavily-doped region and the gate structure are connected to a first voltage.

Abstract: An anti-fuse circuit includes the following: a first transistor, and at least one parasitic transistor and at least one parasitic triode that are connected to the first transistor. The at least one parasitic transistor and the at least one parasitic triode are connected to a first node.

Abstract: The present disclosure provides an electrostatic protection device, and relates to the technical field of semiconductors. The electrostatic discharge protection device includes a first P-type heavily-doped region, a first N-type heavily-doped region, a second N-type heavily-doped region, a second P-type heavily-doped region, and a third N-type heavily-doped region. The first P-type heavily-doped region and the first N-type heavily-doped region are located in a P well, the second P-type heavily-doped region and the third N-type heavily-doped region are located in a first N well, one part of the second N-type heavily-doped region is located in the P well, the other part of the second N-type heavily-doped region is located in first N well, and the P well and the first N well are adjacent to each other and both located in the P-type substrate.

Abstract: Embodiments of the present application provide an electro-static discharge protection circuit and a chip. The electro-static discharge protection circuit includes: a silicon-controlled rectifier, including an anode, a cathode and an electro-static discharge path; a detection unit, connected between the anode and the cathode of the silicon-controlled rectifier, and configured to generate a trigger signal in response to static electricity occurring in a protected chip; and a switching unit, connected to the electro-static discharge path, including an input terminal connected to an output terminal of the detection unit, and configured to turn on the electro-static discharge path based on the trigger signal to discharge an electro-static discharge current.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

Abstract: A method for identifying a latch-up structure includes the following operations. In a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in an N-well is found. A second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-type substrate is found. A second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the N-well is found, the N-well is located on the P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well, and the P-type substrate is identified as the latch-up structure.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit and a chip. The ESD protection circuit is connected between a power supply VDD and a ground VSS, and includes a filter branch, a first inverter group, a switch transistor, a clamp transistor, a feedback transistor, and a second inverter group. The first inverter group has two terminals respectively connected to a first node and a second node. The switch transistor has a gate connected to the second node. The clamp transistor has a gate connected to a fourth node. The feedback transistor has a gate connected to the fourth node. The second inverter group has two terminals respectively connected to a third node and the fourth node.