Abstract: A method for identifying a latch-up structure includes the following: in a chip layout, a first N-type heavily doped region connected to a first input/output pad and located in a P-type substrate is found; a first P-type heavily doped region located in an N-well and a second P-type heavily doped region located in the P-type substrate, both of which are adjacent to the first N-type heavily doped region, are found; a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the N-well is found, wherein the N-well is located on the P-type substrate; and an area formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well and the P-type substrate is identified as the latch-up structure.

Abstract: Methods and apparatus are provided for collaborative partition coding for region based filters. An apparatus includes a video encoder (100) for encoding image data for a plurality of regions in a picture. The video encoder (100) includes multiple filters for filtering the image data based on region partition information for the plurality of regions. The region partition information for the plurality of regions is shared between the multiple filters.

Abstract: A pixel array includes a plurality of sub-pixels, which include first to third sub-pixels. The first and third sub-pixels are alternately arranged along a row direction and form first pixel rows. The first and third sub-pixels, which are in a same column, in the first pixel rows are alternately arranged, and the second sub-pixels are arranged side by side along the row direction and form second pixel rows. Lines sequentially connecting centers of two of the first sub-pixels and two of the third sub-pixels, which are arranged in an array, together form a first virtual quadrilateral, and one of the second sub-pixels is in each first virtual quadrilateral. A straight line in the row direction or in a column direction, which passes through a center of each sub-pixel of at least one of the plurality of sub-pixels, divides the sub-pixel into two parts having areas different from each other.

Abstract: Methods and apparatus are provided for intra coding a block having pixels assigned to groups. An apparatus includes a video encoder for encoding a block in a picture using intra prediction by dividing pixels within the block into at least a first group and a second group and encoding the pixels in the first group prior to encoding the pixels in the second group. A prediction for at least one of the pixels within the second group is obtained by evaluating the pixels within the first group and the second group.

Abstract: Display substrate, display device, high-precision metal mask are provided. Display substrate includes: first, second, and third sub-pixels; in first direction, first and third sub-pixels are alternately arranged to form first sub-pixel rows, second sub-pixels form second sub-pixel rows; in second direction, first and second sub-pixel rows are alternately arranged; two first and two third sub-pixels in two adjacent rows and two adjacent columns form 2*2 array; in the array, two first sub-pixels are in different rows and in different columns, so are the two third sub-pixels, connection lines of centers of two first and two third sub-pixels form virtual quadrilateral, second sub-pixel is within virtual quadrilateral; for multiple distances from centers of two first and two third sub-pixels corresponding to same virtual quadrilateral to center of second sub-pixel, at least two distances are different. Brightness centers of virtual pixels have more uniform distribution.

Abstract: Display substrate, display device, high-precision metal mask are provided. Display substrate includes: first, second, and third sub-pixels; in first direction, first and third sub-pixels are alternately arranged to form first sub-pixel rows, second sub-pixels form second sub-pixel rows; in second direction, first and second sub-pixel rows are alternately arranged; two first and two third sub-pixels in two adjacent rows and two adjacent columns form 2*2 array; in the array, two first sub-pixels are in different rows and in different columns, so are the two third sub-pixels, connection lines of centers of two first and two third sub-pixels form virtual quadrilateral, second sub-pixel is within virtual quadrilateral; for multiple distances from centers of two first and two third sub-pixels corresponding to same virtual quadrilateral to center of second sub-pixel, at least two distances are different. Brightness centers of virtual pixels have more uniform distribution.

Abstract: A method for evaluating a Hot Carrier Injection (HCI) effect of a device is provided. The method includes, a ratio of a substrate current to a drain current of a first device at different gate-source voltages is acquired, and recorded as a first current ratio; a ratio of a substrate current to a drain current of a second device at different gate-source voltages is acquired, and recorded as a second current ratio, the second device is subjected to process parameter adjustment or device parameter adjustment relative to the first device; and an influence of the process parameter adjustment or the device parameter adjustment on an HCI effect of the device is determined based on the second current ratio and the first current ratio.

Abstract: An electrostatic discharge protection structure and a chip are provided. The electrostatic discharge protection structure includes: a semiconductor substrate, an N-type well, a P-type well, a first N-type doped portion, a first P-type doped portion, a second P-type doped portion and a second N-type doped portion. The N-type well and the P-type well are located in the semiconductor substrate. The first N-type doped portion and the second P-type doped portion are located in the P-type well, and the first P-type doped portion and the second N-type doped portion are located in the N-well. The first N-type doped portion has a “T” shape structure, the first P-type doped portion has a “U” shape structure, and a part of the first N-type doped portion is located in a “U” shape opening of the first P-type doped portion.

Abstract: An electrostatic protection circuit and a semiconductor chip are provided. The electrostatic protection circuit is connected to first and second voltage ends. The electrostatic protection circuit includes: a first detection circuit, a control circuit and a discharge transistor. The first detection circuit outputs a first detection signal to the control circuit within a first preset duration after an electrostatic charge appears on the first voltage end; and the control circuit drives the discharge transistor to discharge electrostatic charges under the control of the first detection signal. The electrostatic protection circuit further includes a shutdown circuit. The output end of the shutdown circuit is connected to a control end of the discharge transistor, which is used to output a control signal after a second preset duration after the electrostatic charge appears to shut down the discharge transistor. The second preset duration is greater than or equal to the first preset duration.

Abstract: An Electrostatic Discharge (ESD) protection circuit includes a first discharge path and a second discharge path. The first discharge path is located between a first potential terminal and a second potential terminal. The second discharge path is located between the first potential terminal and the second potential terminal, and is connected to the first discharge path in parallel. The first discharge path and the second discharge path are used for discharging electrostatic charges. At least one of the first discharge path and the second discharge path includes a Silicon Controlled Rectifier (SCR).

Abstract: An electro-static protection structure includes a substrate, a transistor formed in the substrate, and a capacitor. A first pole of the transistor is connected with an electro-static terminal, and a second pole of the transistor and a gate electrode of the transistor are connected with a discharge terminal. A first pole of the capacitor is connected with the substrate, and a second pole of the capacitor is connected with the electro-static terminal.

Abstract: An electro-static discharge (ESD) protection circuit is electrically connected to a first pad and a second pad. The ESD protection circuit includes an ESD transistor having a control terminal, a first terminal electrically connected to the first pad, a second terminal electrically connected to the second pad, and a substrate end; and an electro-static pulse detection circuit having an upper terminal electrically connected to the first pad, a lower terminal electrically connected to the second pad, and an output terminal electrically connected to the control terminal and the substrate end of the ESD transistor.

Abstract: A power tool includes a brushless motor including several windings, a drive circuit for driving the brushless motor, a detection device for detecting the brushless motor so as to obtain a load parameter corresponding to a load of the brushless motor, and a controller for outputting a first control signal to reduce current of the brushless motor in a first slope when the load parameter exceeds a first preset range.

Abstract: Methods and apparatus are provided for signaling intra prediction for large blocks for video encoders and decoders. An apparatus includes a video encoder (400) for encoding picture data for at least one large block in a picture by signaling intra prediction for the at least one large block. The intra prediction is signaled by selecting a basic coding until size and assigning a single spatial intra partition type for the basic coding until size. The single spatial intra partition type is selectable from among a plurality of spatial intra partition types. The at least one large block has a large block size greater than a block size of the basic coding unit. The intra prediction is hierarchical layer intra prediction and is performed for the at least one large block by at least one of splitting from the large block size to the basic coding until size and merging from the basic coding unit size to the large block size.

Abstract: There is provided a pixel array including a plurality of sub-pixels, which include first sub-pixels, second sub-pixels, and third sub-pixels. The first and third sub-pixels are alternately arranged along a row direction and form a plurality of first pixel rows, the first and third sub-pixels, which are in a same column, in the plurality of first pixel rows are alternately arranged, and the second sub-pixels are arranged along the row direction and form second pixel rows. Lines sequentially connecting centers of any two of the first sub-pixels and any two of the third sub-pixels, which are arranged in an array, together form a first virtual quadrilateral, and one of the second sub-pixels is in each first virtual quadrilateral. At least one interior angle of the first virtual quadrilateral is not 90°. At least one of the first, second and third sub-pixels has a corner circularly or rectilinearly chamfered.

Abstract: The present disclosure provides a pixel arrangement structure, a fine metal mask set and a display apparatus. The pixel arrangement structure includes a plurality of sub-pixel repetition units along a first direction or a second direction. The plurality of sub-pixel repetition units each form a plurality of pixel units. The sub-pixel repetition units each include one or more first color sub-pixels, one or more second color sub-pixels and one or more third color sub-pixels. Each of the first color sub-pixels and each of the second color sub-pixels independently belong to one pixel unit respectively, and each of the third color sub-pixels is shared by two pixel units. The first direction intersects with the second direction.

Abstract: According to some embodiments, systems and methods are provided including an automatic testing (AT) framework including an automatic testing (AT) tool and an AT engine; a processing unit coupled to the automatic testing framework to: generate a JSON file, wherein the JSON file is a test case; upload the generated test case to a database of the AT framework; and execute the test case in response to uploading, wherein execution further comprises: reading the test case from the database; validating the JSON file matches a JSON schema; mocking the test case to generate an executable test, including one or more nullable values based on the generated JSON file; executing the executable test to generate an output; and verifying the generated output by comparing the generated output to an expected output in the test case. Numerous other aspects are provided.

Abstract: The present invention relates to an electrostatic protection circuit for protecting an internal circuit. The electrostatic protection circuit includes: a first circuit connected between a power pad and an input pad and configured to discharge a first electrostatic current; a second circuit connected between the input pad and a ground pad and configured to discharge a second electrostatic current; a third circuit connected between the power pad and the input pad and configured to discharge a third electrostatic current; a fourth circuit connected between the power pad and the ground pad and configured to discharge a fourth electrostatic current; a fifth circuit connected between the input pad and the ground pad and configured to discharge a fifth electrostatic current; and a sixth circuit connected between the ground pad and the power pad and configured to discharge a sixth electrostatic current.