Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate is provided with a peripheral area and an array area; an insulation layer is formed on the substrate; a first mask layer with a first mask pattern is formed on the insulation layer; the insulation layer is etched by taking the first mask layer as a mask, to form a contact hole in the array area; a first electrode layer is formed; a second mask layer with a second mask pattern is formed, in which the second mask layer is arranged on the first electrode layer; and the first electrode layer and the first mask layer are etched by taking the second mask layer as a mask until the insulation layer in the array area is exposed, in which a remaining portion of the first electrode layer forms a lower electrode layer.

Abstract: Embodiments of the present disclosure provide a patterning method and a semiconductor structure. The method includes: providing a substrate, wherein the substrate includes adjacent storage regions and peripheral circuit regions; forming, on the substrate, a pattern transfer layer, the pattern transfer layer having a plurality of first hard masks, wherein the first hard masks extend along a first direction and are spaced apart from each other; forming a barrier layer on the pattern transfer layer; forming, on the barrier layer, a plurality of second hard masks, the plurality of second hard masks extending along a second direction, wherein the second hard masks are spaced apart from each other, and the second hard masks are located in the storage regions and second hard masks close to the peripheral circuit regions have structural defects.

Abstract: A method for manufacturing a semiconductor structure includes: a first mask layer is formed on a dielectric layer, in which a first etching hole extending along a first direction parallel to the dielectric layer is formed in the first mask layer; a side of the first mask layer away from the dielectric layer is planarized; a second mask layer is formed on the first mask layer, in which a second etching hole extending along a second direction parallel to the dielectric layer is formed in the second mask layer, the first etching hole and the second etching hole constitute an etching hole; and the dielectric layer is etched along the etching hole to form the capacitor hole.

Abstract: The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Abstract: A manufacturing method of a semiconductor structure is disclosed, which includes: an initial structure is provided; a filling layer covering a spacer is formed on the initial structure; a filling layer with a first preset thickness is removed at a high first etching rate through a first etching process, then a filling layer with a second preset thickness is removed at a low second etching rate through a second etching process, and the partial spacer is exposed; and the filling layer and the spacer are patterned.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

Abstract: A method for manufacturing a memory includes: providing a substrate, capacitor contact pads being formed in the substrate; forming a laminated structure on the substrate, the laminated structure including a first laminated structure formed on the substrate and a second laminated structure formed on the first laminated structure; forming first through holes in the second laminated structure; forming a protective layer on side walls of the first through holes, the protective layer in the first through holes enclosing second through holes; and etching the first laminated structure along the second through holes to form third through holes, the third through holes exposing the capacitor contact pads.

Abstract: A method for controlling vehicle parking, includes: obtaining, by a processor, a current vehicle speed and a current vehicle control level of a vehicle; obtaining, by the processor, a target vehicle speed of the vehicle, and obtaining a target vehicle control level of the vehicle according to the current vehicle control level; obtaining, by the processor, a first vehicle control level according to the current vehicle speed, the target vehicle speed, the current vehicle control level, and the target vehicle control level; and controlling, by the processor, the vehicle to run according to the first vehicle control level.

Abstract: A squeeze-enhanced axial transformer (SeaFormer) for mobile semantic segmentation is disclosed, including a shared stem, a context branch, a spatial branch, a fusion module and a light segmentation head, wherein the shared stem produces a feature map; the context branch obtains context-rich information; the spatial branch obtains spatial information; the fusion module incorporates the features in the context branch into the spatial branch; and the light segmentation head receives the feature from the fusion module and output the results. This application is also related to the layer of the SeaFormer, as well as methods thereof.

Abstract: An information processing method, apparatus, and device, and a storage medium, relating to the technical field of games. The method includes: detecting, by means of a first collider of a virtual object in a game scene, whether an interaction occurs between the virtual object and a virtual vehicle; calculating a second speed of the virtual vehicle after interaction and state information of the virtual object according to attribute information of the virtual vehicle, a first speed of the virtual vehicle before interaction, and attribute information of the virtual object; adding a second collider for simulating the motion of the virtual object to the virtual object; and according to the second speed of the virtual vehicle after interaction and the state information of the virtual object, on the basis of the second collider, simulating the motion of the virtual object after interaction with the virtual vehicle.

Abstract: Embodiments provide a method for fabricating an array structure of a columnar capacitor and a semiconductor structure. In the method, before a mask layer is removed, a photoresist layer is filled to adjust a thickness of the mask layer in a peripheral region and a thickness of the mask layer in an array region to be equal, thereby preventing a top support layer from being worn due to impacts of different thicknesses of the mask layers on a thickness of the top support layer. In addition, in the method, a third sacrificial layer and an auxiliary layer are further formed to perform dual protection on the top support layer, thereby preventing the top support layer from being thinned in subsequent processes, to increase support strength of the top support layer, thereby further preventing the columnar capacitor from tilting due to insufficient support strength of the top support layer.

Abstract: An information processing method, apparatus, and device, and a storage medium, relating to the technical field of games. The method includes: detecting, by means of a first collider of a virtual object in a game scene, whether an interaction occurs between the virtual object and a virtual vehicle; calculating a second speed of the virtual vehicle after interaction and state information of the virtual object according to attribute information of the virtual vehicle, a first speed of the virtual vehicle before interaction, and attribute information of the virtual object; adding a second collider for simulating the motion of the virtual object to the virtual object; and according to the second speed of the virtual vehicle after interaction and the state information of the virtual object, on the basis of the second collider, simulating the motion of the virtual object after interaction with the virtual vehicle.

Abstract: The present disclosure provides a method of forming a capacitor array and a semiconductor structure. The method of forming a capacitor array includes: providing a substrate, the substrate including an array region and a non-array region, wherein a base layer and a dielectric layer are formed in the substrate, and a first barrier layer is formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of each of the first array definition layer and the second array definition layer; patterning the dielectric layer and the second array definition layer by using the pattern transfer layer as a mask, and forming a capacitor array located in the array region.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate, where the stack includes sacrificial layers and supporting layers; forming a first photoresist layer on the stack; exposing the first photoresist layer, and developing to remove the first photoresist layer on the incomplete die region; and etching the stack by using the first photoresist layer on the complete die region as a mask.

Abstract: The present disclosure provides an etching defect detection method, relating to the field of semiconductor technology. The detection method includes: providing a substrate, and sequentially forming a conductive layer and a dielectric layer on the substrate; etching the dielectric layer to form a trench structure; taking the conductive layer as a cathode, and filling the trench structure with an electroplating layer by an electroplating process, to form a product to-be-detected; and testing the product to-be-detected by a defect density detection assembly, to obtain a top-view image of the trench structure, and determining an etching defect of the product to-be-detected according to the top-view image. The etching defect detection method can improve the accuracy of defect identification and prevent a capacitor from failing due to suspension.

Abstract: System and methods for automatically publishing Representational State Transfer (REST) Application Programming Interface (API) changes in a cloud environment are described. A publish/subscribe server (PSS) may receive from a subscriber a customized request for monitoring a registered REST API supported by a REST service provider (RSP) and registered with the PSS. The subscriber is configured to invoke the registered REST API at the RSP. The PSS may monitor the registered REST API for any changes at the RSP based on the customized request. In response to a determination that the registered REST API is changed at the RSP, the PSS may generate a REST API change report indicating a change event occurred to the registered REST API at the RSP after being registered with the PSS. The PSS may then transmit the REST API change report to the subscriber. The subscriber is configured to not invoke the registered REST API at the RSP based on the REST API change report.

Abstract: A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

Abstract: The present application relates to a mask structure, a semiconductor structure and methods for manufacturing the same. The method for manufacturing a mask structure includes: dividing an overall structure into two regions, and developing the array region and the periphery region with a negative photoresist.

Abstract: The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Abstract: Embodiments provide a method for fabricating an array structure of a columnar capacitor and a semiconductor structure, relating to the field of semiconductor manufacturing technology. In the method, before a mask layer is removed, a thickness of the mask layer in the peripheral region is first adjusted to be equal to a thickness of the mask layer in the array region, thereby avoiding damage to a top support layer caused by different thicknesses of the mask layer. Moreover, in the method, a thickness of the top support layer is increased by means of a supplementary support layer, to increase support strength of the top support layer, thereby further preventing occurrence of tilt of the columnar capacitor due to insufficient support strength of the top support layer.