Abstract: A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

Abstract: A method for forming a capacitor array structure includes the following operations. A base is formed, which includes a substrate, a stack structure located on the substrate and a mask layer located on the stack structure in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided. The stack structure is etched along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate. A conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer is formed. The conductive layer and the mask layer at a top surface of the stack structure are removed, and the conductive layer remaining in the capacitor hole forms a lower electrode.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

Abstract: A driving control method and apparatus for a vehicle, and a vehicle are provided, and relate to the field of vehicle control. The vehicle includes at least two carriages, and the driving control method includes the following steps: obtaining battery level information of a power battery corresponding to each of the carriages; obtaining at least one of a level allocated to each carriage or a payload allocated to each carriage according to the battery level information of the power battery corresponding to each carriage; and obtaining an output torque of each carriage according to the at least one of the level allocated to each carriage or the payload allocated to each carriage.

Abstract: The disclosure provides a method for manufacturing a memory and the memory. The method includes that a laminated structure is formed on a substrate, in which the laminated structure comprises sacrificial layers and supporting layers arranged alternately, a top layer of the laminated structure is a supporting layer, and a supporting layer between two sacrificial layers is provided with intermediate holes filled with a sacrificial material; capacitor holes penetrating through the laminated structure are formed; a first polar plates are formed on the hole walls and the hole bottoms of the capacitor holes; areas corresponding to the intermediate holes in the supporting layer located on the top layer of the laminated structure are removed to form capacitor opening holes, which exposes a sacrificial layer; and all the sacrificial layers and all the sacrificial material are removed through the capacitor opening holes.

Abstract: The present application provides a manufacturing method of a memory. The manufacturing method includes: providing a substrate, where the substrate includes a core region and a peripheral region, and a first barrier layer is provided in the core region; laminating and forming a first conductive layer and a first mask layer on the substrate in sequence; etching the first mask layer, the first conductive layer, and the first barrier layer in the core region, to form a first etched hole; etching the substrate along the first etched hole, to form a bit line contact hole; removing the first mask layer and the first conductive layer in the core region and located around the bit line contact hole; and forming a bit line contact in the bit line contact hole.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a base, wherein the base is provided with an active region; forming a gate layer on the base; forming isolation structures on a periphery of the gate layer, wherein in a direction away from the gate layer, each of the isolation structures at least includes a hollow portion and an isolation portion; forming an insulating structure on top surfaces of the isolation structures; forming contact plugs, wherein the contact plugs penetrate the insulating structure; an end of each of the contact plugs close to the base is electrically connected to the active region; each of the contact plugs is located on a side of each of the isolation structures away from the gate layer.

Abstract: Embodiment relates to a method for fabricating a semiconductor structure. The method includes: forming a first pattern on the first region and forming a second pattern on the second region, wherein the first pattern includes a plurality of first sub-patterns, a first gap is provided between adjacent two of the plurality of first sub-patterns, a width of the first gap is a first pitch, and wherein the second pattern includes a plurality of second sub-patterns, a second gap is provided between adjacent two of the plurality of second sub-patterns, a width of the second gap is a second pitch, and the second pitch is greater than the first pitch; forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern; and removing the first pattern and the second pattern.

Abstract: The present application provides a manufacturing method of a memory. The manufacturing method includes: providing a substrate, where the substrate includes a core region and a peripheral region, and a first barrier layer is provided in the core region; laminating and forming a first conductive layer and a first mask layer on the substrate in sequence; etching the first mask layer, the first conductive layer, and the first barrier layer in the core region, to form a first etched hole; etching the substrate along the first etched hole, to form a bit line contact hole; removing the first mask layer and the first conductive layer in the core region and located around the bit line contact hole; and forming a bit line contact in the bit line contact hole.

Abstract: A method for manufacturing a mask pattern includes the following operations. A pattern transfer layer, an etching stopping layer, a sacrificial layer and a hard mask layer that are stacked from bottom up are formed. The hard mask layer and the sacrificial layer are patterned to obtain sacrificial patterns which expose the etching stopping layer. Side wall structures are formed on the side walls of the sacrificial patterns. The sacrificial patterns are removed. Filling layers are formed between the side wall structures, and the etching selection ratio of the side wall structures to the filling layers is greater than 100. The side wall structures are removed to form an initial mask pattern. The etching stopping layer and the pattern transfer layer are etched based on the initial mask pattern to transfer a pattern of the initial mask pattern to the pattern transfer layer to obtain a target mask pattern.

Abstract: Embodiments of the present disclosure provide a patterning method and a semiconductor structure. The method includes: providing a substrate, wherein the substrate includes adjacent storage regions and peripheral circuit regions; forming, on the substrate, a pattern transfer layer, the pattern transfer layer having a plurality of first hard masks, wherein the first hard masks extend along a first direction and are spaced apart from each other; forming a barrier layer on the pattern transfer layer; forming, on the barrier layer, a plurality of second hard masks, the plurality of second hard masks extending along a second direction, wherein the second hard masks are spaced apart from each other, and the second hard masks are located in the storage regions and second hard masks close to the peripheral circuit regions have structural defects.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, including: an insulating layer includes a first dielectric layer and a second dielectric layer, a protective layer covers an upper surface of the second dielectric layer and a bottom and sidewalls of the first trench; removing part of the protective layer to expose at least part of a surface of the second dielectric layer; removing the second dielectric layer by a first wet etching process, the first wet etching process has a first etch selectivity of a material of the second dielectric layer to that of the first dielectric layer; and removing the protective layer by a second wet etching process, the second wet etching process has a second etch selectivity of a material of the protective layer to that of the first dielectric layer, and the second etch selectivity is greater than the first etch selectivity.

Abstract: The present application provides a method for preparing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method for preparing a semiconductor structure includes: providing a base; forming a support layer having capacitor holes and electric contact structures; forming a first dielectric layer in the capacitor holes, the first dielectric layer surrounding first intermediate holes; forming a first electrode layer in the first intermediate holes, the first electrode layer filling the first intermediate holes; removing part of the support layer to form second intermediate holes; forming a second dielectric layer in the second intermediate holes, the first dielectric layer and the second dielectric layer forming a dielectric layer; and, forming a second electrode layer on the dielectric layer.

Abstract: A method for manufacturing a mask structure includes: patterning a sacrificial layer and a second dielectric layer, so as to form pattern structures each including a first pattern and a second pattern, and a width of a lower portion of the pattern structures is less than a width of a upper portion of the pattern structures; forming an initial mask pattern on sidewalls of each of the plurality of pattern structures; filling a first filling layer between adjacent initial mask patterns located on the sidewalls of different pattern structures; removing the second patterns and the initial mask pattern located on sidewalls of each of the plurality of second patterns; removing the first filling layer and the first patterns, so as to form first mask patterns; and forming second mask patterns on the first mask patterns.

Abstract: The embodiments of the present disclosure belong to the technical field of semiconductor manufacturing, and relate to a semiconductor structure and a method for manufacturing a semiconductor structure. Each of a plurality of storage structures in the semiconductor structure includes a plurality of capacitor structures stacked in a direction perpendicular to a substrate, each of the plurality of capacitor structures includes a bottom plate and an top plate which are arranged opposite to each other, and a first dielectric layer located between the bottom plate and the top plate, and the bottom plate and the top plate are both parallel to the substrate, all bottom plates in each of the plurality of storage structures are electrically connected, and all top plates in each of the plurality of storage structures are electrically connected; the bottom plate and the top plate extend in a plane parallel to the substrate.

Abstract: A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a bit line located on the substrate; and a support layer located on the substrate, wherein the support layer includes a first support segment and a second support segment, the first support segment and the second support segment are both connected to the bit line, and the bit line is located between the first support segment and the second support segment.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate, and forming a first sacrificial layer on the substrate, where the first sacrificial layer includes a first sacrificial dielectric layer and a second sacrificial dielectric layer; patterning the first sacrificial layer, and forming first intermediate pattern structures that are arranged at intervals, where a first gap is provided between two adjacent first intermediate pattern structures; forming a first spacer pad layer in the first gap, where the first spacer pad layer covers sidewalls of each of the two adjacent first intermediate pattern structures and a bottom of the first gap; removing the first spacer pad layer at the bottom of the first gap, and the second sacrificial dielectric layer; and removing the first sacrificial dielectric layer, to form first pattern structures.

Abstract: A method for forming a semiconductor structure includes: forming a base including a substrate, capacitor contacts in the substrate, a laminated structure disposed on a surface of the substrate capacitor holes penetrating through the laminated structure and exposing the respective capacitor contacts, the laminated structure including a plurality of support layers and at least one sacrificial layer which are alternately stacked along a direction perpendicular to the substrate, and a lower electrode layer covering inner walls of the capacitor holes; forming a protective layer covering a surface of the lower electrode layer; etching part of the support layer to expose the sacrificial layer; and removing all the sacrificial layers and all the protective layer to expose the lower electrode layer.

Abstract: A method for preparing a semiconductor structure, and a semiconductor structure are provided. In a prepared first pattern structure, a thickness of a first insulating layer is equal to a thickness of a second insulating layer, and a thickness of a third insulating layer is equal to a thickness of a fourth insulating layer.