Abstract: A method for manufacturing a color resist is disclosed. According to the method, a mask is moved so that an alignment mark is aligned with marks of a black matrix layer respectively. Each color resist and a corresponding color block are formed on the black matrix layer by the mask, and a position of each color resist is checked according to a positional relationship between a corresponding color block and hollowed-out region. A distance between a first mark and a second mark and a distance between a first mark and a third mark are configured in such manner that the color blocks do not overlap with one another. Therefore, the color blocks do not overlap with one another while a size thereof does not change.

Abstract: A method of preparing IGZO thin film transistor is provided. The method includes. step S1, using a first mask on a first metal layer to form a grid electrode, and sequentially forming grid insulating layer, IGZO semiconducting layer and second metal layer on grid electrode; step S2, coating photoresist layer on second metal layer, and exposure developing photoresist layer by second mask, and simultaneously etching second metal layer and IGZO semiconducting layer by hydrogen peroxide, and second metal layer is formed to source electrode and drain electrode by etching; step S3, forming passivation layer on source electrode and drain electrode, and forming a via hole above drain electrode by third mask; step S4, forming pixel electrode on passivation layer by fourth mask, and pixel electrode is connecting to drain electrode by via hole.

Abstract: The present disclosure relates to an array substrate and the manufacturing method thereof, and a liquid crystal panel. The method includes forming a first metal substrate on a substrate; adopting a first mask to etch the first metal substrate to form a gate; forming a gate insulation layer, an active layer, and a second metal layer on the first metal layer in sequence; and adopting a second mask to etch the second metal layer and the active layer to form a source, a drain, and a pixel electrode. In this way, only two masks are adopted in the manufacturing process. Thus, the manufacturing process is enhanced, and the cost of the product is reduced.

Abstract: A method of preparing IGZO thin film transistor is provided. The method includes. step S1, using a first mask on a first metal layer to form a grid electrode, and sequentially forming grid insulating layer, IGZO semiconducting layer and second metal layer on grid electrode; step S2, coating photoresist layer on second metal layer, and exposure developing photoresist layer by second mask, and simultaneously etching second metal layer and IGZO semiconducting layer by hydrogen peroxide, and second metal layer is formed to source electrode and drain electrode by etching; step S3, forming passivation layer on source electrode and drain electrode, and forming a via hole above drain electrode by third mask; step S4, forming pixel electrode on passivation layer by fourth mask, and pixel electrode is connecting to drain electrode by via hole.

Abstract: A color-filter on array (COA) type array substrate is provided. Sub-pixels connected to an identical data line include red sub-pixels R, green sub-pixels G, and blue sub-pixels B, all of which are the same in number. The sub-pixels connected to an identical scan line include the red sub-pixels R, the green sub-pixels G, and the blue sub-pixels B, all of which are the same in number.

Abstract: The present invention provides a TFT substrate. The TFT substrate includes: a first display area and a second display area that are sequentially arranged in a vertical direction. Main pixel electrodes and sub pixel electrodes of the first display area are arranged in mirror symmetry with respect to main pixel electrodes and sub pixel electrodes of the second display area, respectively, about a horizontal division line of the first display area and the second display area. A scanning direction of the first display area is such that scanning is conducted from the side that the sub pixel electrode of one of the sub-pixels of the first display area is located toward the side that the main pixel electrode of the one of the sub-pixels is located. A scanning direction of the second display area is opposite to the scanning direction of the first display area.

Abstract: The present disclosure relates to an array substrate, a manufacturing method thereof and a liquid crystal display (LCD). The manufacturing method of array substrates includes forming a first metal layer on a substrate, etching the first metal layer via a first mask to form a gate and a common electrode, forming a gate insulation layer, an active layer, and a second metal layer on the first metal layer in sequence, etching the second metal layer and the active layer via a second mask to form a source, a drain, and a pixel electrode. As such, the manufacturing process of the array substrate may only require two masks, the productivity may be improved, and the costs may be reduced.

Abstract: A pixel unit and a display substrate are provided. The pixel unit has at least two sub-pixels arranged along a first direction or a second direction within a liquid crystal display panel, and each of the sub-pixels comprises a first area, a second area, and a third area, wherein a source/drain of the third-area thin film transistor connects to a third-area common electrode, and the third-area common electrode connects to a second input.

Abstract: The invention provides an array substrate, each sub-pixel comprising: a control TFT and a pixel electrode connected to control TFT; the pixel electrode comprising: a main region pixel electrode and a secondary region pixel electrode, layout with a gap in-between, and a first connection electrode electrically connected to the main region pixel electrode and the secondary region pixel electrode; the main and secondary region pixel electrodes being of special shape slit structure, the main region branch electrodes having a width smaller than width of the secondary region branch electrodes, the main region slit having a width smaller than width of the secondary region slit. The structural difference in the main and secondary region pixel electrodes is used to improve color shift, leading to reducing the number of TFTs in each pixel, improving pixel aperture ratio, reduces difficulty in balance control of best common voltage between main and secondary regions.

Abstract: A method for manufacturing a color resist is disclosed. According to the method, a mask is moved so that an alignment mark is aligned with marks of a black matrix layer respectively. Each color resist and a corresponding color block are formed on the black matrix layer by the mask, and a position of each color resist is checked according to a positional relationship between a corresponding color block and hollowed-out region. A distance between a first mark and a second mark and a distance between a first mark and a third mark are configured in such manner that the color blocks do not overlap with one another. Therefore, the color blocks do not overlap with one another while a size thereof does not change.

Abstract: The present application discloses an array substrate and a method for fabricating the same, and a liquid crystal display panel. A transparent electrode and a second passivation layer are disposed between a planarization layer and a pixel electrode, the transparent electrode is disposed between the planarization layer and the second passivation layer, the pixel electrode and the transparent electrode are insulated and disposed in stack by the second passivation layer sandwiched therebetween, and forms a storage capacitor of the array substrate.

Abstract: The present disclosure provides a pixel circuit and a liquid crystal display circuit. The pixel circuit comprises a gate line, a data line, a first common line, a second common line, a first primary field-effect transistor (FET), a second primary FET, a first secondary FET, and a second secondary FET. A voltage of the first common line is different from a voltage of the second common line.

Abstract: The present disclosure relates to an array substrate and a display panel. The array substrate includes a first driving chip and a second driving chip configured on the top and the bottom of the array substrate respectively. Data lines on the first 6a number of columns connect to the first pins of the first driving chip, and data lines on the second 6a number of columns connect to the second pins of the second driving chip, and remaining data lines connects to the first pins and the second pins in an alternating manner. Such that, three sub-pixels within the same pixel may be driven by the driving chip configured on the same side, and the adjacent first pins and the adjacent second pins may output the signals with different polarities. So as to achieve the dot inversion of the polarities among the sub-pixels.

Abstract: The present invention provides an array substrate and a LCD panel. The array substrate, which comprises: a display area and a peripheral area, wherein the display area has at least two types of pixel electrodes, gate lines and data lines, which are arranged in rows and columns, one of the gate line is connected to two columns of the corresponding pixel electrodes and two of the data lines are connected to one row of the corresponding pixel electrodes. By the above description, the present invention can resolve requirements of testing HG2D (half-gate two-data line) drive circuit.

Abstract: The present invention provides a TFT substrate. The TFT substrate includes: a first display area and a second display area that are sequentially arranged in a vertical direction. Main pixel electrodes and sub pixel electrodes of the first display area are arranged in mirror symmetry with respect to main pixel electrodes and sub pixel electrodes of the second display area, respectively, about a horizontal division line of the first display area and the second display area. A scanning direction of the first display area is such that scanning is conducted from the side that the sub pixel electrode of one of the sub-pixels of the first display area is located toward the side that the main pixel electrode of the one of the sub-pixels is located. A scanning direction of the second display area is opposite to the scanning direction of the first display area.

Abstract: The present disclosure provides a pixel unit, an array substrate and a display panel. The pixel unit includes a main pixel portion and a secondary pixel portion electrically connected to the main pixel portion, wherein the main pixel portion includes a first horizontal trunk, a first vertical trunk and first branches; the secondary pixel portion includes a second horizontal trunk, a second vertical trunk and second branches; wherein, an acute angle between the first branches and the first horizontal trunk is different from an acute angle between the second branches and the second horizontal trunk. The implementation of the present disclosure may make the liquid crystal molecules in a pixel unit to have different inclination angle so as to improve the side viewing of the display panel.

Abstract: The present disclosure provides a pixel circuit and a liquid crystal display circuit. The pixel circuit comprises a gate line, a data line, a first common line, a second common line, a first primary field-effect transistor (FET), a second primary FET, a first secondary FET, and a second secondary FET. A voltage of the first common line is different from a voltage of the second common line.

Abstract: The invention provides an 8-domain pixel structure, comprising: a plurality of sub-pixels arranged in array in LCD panel, each sub-pixel being divided into main and sub areas, a scan line for each sub-pixel row, a data line for each sub-pixel column; comprising: main area TFT, main area storage capacitor, sub area TFT, and sub area storage capacitor; main area storage capacitor formed by first main area storage electrode in main area and corresponding common electrode; sub area storage capacitor formed by sub area storage electrode in sub area with second main area storage electrode in main area and corresponding common electrode, sub area storage electrode and second main area storage electrode electrically connected to each other across scan line. The invention achieves the object of controlling voltage difference ratio between the main and sub areas, and the best common voltage problem areas does not exist.

Abstract: The present invention provides a manufacture method of an array substrate and an array substrate manufactured by the method. By sequentially forming the first passivation layer and the flat layer, and then implementing patterning process and anneal process to the flat layer, in the anneal process to the flat layer, the flat layer and the source/the drain cannot contact with each other due to the first passivation layer inbetween, and thus, no reaction of generating complex happens, which is beneficial for promoting the electrical property of the array substrate and realizing the signal conduction; in comparison with prior art, the present invention can decrease at least one mask in advance, which is a advantage to raise the process result, to decrease the process time and to reduce the production cost. In the array substrate, the signal transmission is smooth, and the substrate possesses the great electrical property.

Abstract: The present invention provides an array substrate and a display device. The array substrate of the present invention includes an ESD area that is provided with a color resist layer to cover and shield the ESD assembly, and thus cover and shield TFTs, to effectively isolate moisture, protect the TFTs from corrosion by the moisture and keep excellent electrical properties of the TFTs, so as to effectively reduce the potential risk of shorting caused by static electricity. The display device of the present invention involves the above array substrate to effectively isolate moisture, protect TFTs from corrosion by the moisture and keep excellent electrical properties of the TFTs, so as to effectively reduce the potential risk of shorting caused by static electricity.