Abstract: The present invention provides an etching solution of IGZO film layer and an etching method of the same. The etching solution of IGZO film layer of the present invention comprises an acid, a phosphate, a hydrogen peroxide, and water; and the PH value of the etching solution of IGZO film layer is no more than 5, which are capable of effectively controlling the rate of the etching solution to make the etching rate uniform, then the IGZO film layer is etched stably without introducing impurities affecting the electric characteristic of the IGZO, to raise the stability of the IGZO-TFT device. The etching method of IGZO film layer, with applying the etching solution mentioned above, which is capable of effectively controlling the rate of the etching solution to make the etching rate uniform, then the IGZO film layer, is etched stably without introducing impurities affecting the electric characteristic of the IGZO, to raise the stability of the IGZO-TFT device.

Abstract: The present disclosure relates to an array substrate and a display panel. The array substrate includes a first driving chip and a second driving chip configured on the top and the bottom of the array substrate respectively. Data lines on the first 6a number of columns connect to the first pins of the first driving chip, and data lines on the second 6a number of columns connect to the second pins of the second driving chip, and remaining data lines connects to the first pins and the second pins in an alternating manner. Such that, three sub-pixels within the same pixel may be driven by the driving chip configured on the same side, and the adjacent first pins and the adjacent second pins may output the signals with different polarities. So as to achieve the dot inversion of the polarities among the sub-pixels.

Abstract: A test lead wire structure for connecting signal lines in a display device with test lines outside, includes a first insulating layer, a second insulating layer, first lead wires, and second lead wires. The projections of the first lead wires on the second insulating layer and the projections of the second lead wires on the second insulating layer are alternately disposed. During the cutting operation, short circuits are effectively prevented from occurring between the different test lead wires.

Abstract: The present disclosure relates to an array substrate and the manufacturing method thereof, and a liquid crystal panel. The method includes forming a first metal substrate on a substrate; adopting a first mask to etch the first metal substrate to form a gate; forming a gate insulation layer, an active layer, and a second metal layer on the first metal layer in sequence; and adopting a second mask to etch the second metal layer and the active layer to form a source, a drain, and a pixel electrode. In this way, only two masks are adopted in the manufacturing process. Thus, the manufacturing process is enhanced, and the cost of the product is reduced.

Abstract: The present disclosure relates to an array substrate, a manufacturing method thereof and a liquid crystal display (LCD). The manufacturing method of array substrates includes forming a first metal layer on a substrate, etching the first metal layer via a first mask to form a gate and a common electrode, forming a gate insulation layer, an active layer, and a second metal layer on the first metal layer in sequence, etching the second metal layer and the active layer via a second mask to form a source, a drain, and a pixel electrode. As such, the manufacturing process of the array substrate may only require two masks, the productivity may be improved, and the costs may be reduced.

Abstract: The present disclosure provides a COA substrate which includes a plurality of thin film transistors arranged in a matrix, a plurality of data lines, and a plurality of scan lines. The data lines intersect perpendicularly with the data lines. Plural gaps are formed in portions of the data lines which intersect with the scan lines. The gaps cross the scan lines. Each of the gaps is connected via a jumper wire. The jumper wire is electrically connected to one of the data lines via through holes. The portions of the data lines which intersect with the scan lines are replaced by the jumper wires in a different layer. A thickness between the jumper wires and the scan lines is increased, and thus parasitic capacitances in the portions are reduced.

Abstract: The disclosure provides an array substrate, including a substrate, a common line, a separation layer, a gate line layer, a first insulation layer, a data line layer, a second insulation layer, a first transparent electrode, a third insulation layer and a second transparent electrode overlapped in sequence, a first via hole is defined in the separation layer, a second via hole is defined in the first insulation layer, a third via hole and a fourth via hole communicated with the second via hole are defined in the second insulation layer, the first transparent electrode penetrates the first via hole, the second via hole and the fourth via hole to connect with the common line, a fifth via hole communicated with the third via hole is defined in the third insulation layer, the second transparent electrode is connected to the data line layer.

Abstract: The present invention provides a TFT substrate manufacturing method, which uses a half tone mask or a gray tone mask to pattern a passivation layer so that a pixel electrode via and a groove-patterned passivation layer can be formed with one mask. And, a transparent conductive material can be deposited on and in compliance with the passivation layer to form a pixel electrode. The pixel electrode requires no mask for patterning, and entire manufacture of a TFT substrate requires only three masks, without the need of indium tin oxide lift-off technique, making the difficulty of manufacturing low and efficiency high.

Abstract: The present application discloses an array substrate and a method for fabricating the same, and a liquid crystal display panel. A transparent electrode and a second passivation layer are disposed between a planarization layer and a pixel electrode, the transparent electrode is disposed between the planarization layer and the second passivation layer, the pixel electrode and the transparent electrode are insulated and disposed in stack by the second passivation layer sandwiched therebetween, and forms a storage capacitor of the array substrate.

Abstract: A color-filter on array (COA) type array substrate is provided. Sub-pixels connected to an identical data line include red sub-pixels R, green sub-pixels G, and blue sub-pixels B, all of which are the same in number. The sub-pixels connected to an identical scan line include the red sub-pixels R, the green sub-pixels G, and the blue sub-pixels B, all of which are the same in number.

Abstract: The invention provides an LCD pixel driver circuit and TFT substrate. The LCD pixel driver circuit comprises: a plurality of sub-pixels arranged in an array, each sub-pixel comprising: a main region TFT, a main region charge-sharing TFT, a secondary region TFT, a secondary charge-sharing TFT, a main region storage capacitor, a first secondary region storage capacitor, a main region LCD capacitor, and a secondary LC capacitor; the main and secondary region charge-sharing TFTs receiving respective the first and second array substrate common voltages. Through adjusting the first and second array substrate common voltages to adjust the LCD common voltage, the present invention can reduce the difficulty of controlling the best common voltage of LCD, and improve the control of the best common voltage efficiency and display effect.

Abstract: The invention provides an 8-domain pixel structure, comprising: a plurality of sub-pixels arranged in array in LCD panel, each sub-pixel being divided into main and sub areas, a scan line for each sub-pixel row, a data line for each sub-pixel column; comprising: main area TFT, main area storage capacitor, sub area TFT, and sub area storage capacitor; main area storage capacitor formed by first main area storage electrode in main area and corresponding common electrode; sub area storage capacitor formed by sub area storage electrode in sub area with second main area storage electrode in main area and corresponding common electrode, sub area storage electrode and second main area storage electrode electrically connected to each other across scan line. The invention achieves the object of controlling voltage difference ratio between the main and sub areas, and the best common voltage problem areas does not exist.

Abstract: The present invention provides a manufacture method of an array substrate and an array substrate manufactured by the method. By employing one mask to achieve the via opening process to the flat layer and the first passivation layer, one mask can be saved to decrease the production cost and to reduce the process time; the conductive connection layer covering the first via on the flat layer and the second via on the first passivation layer are formed at the same time while forming the common electrode, and thus to prevent that the source/the drain and the flat layer to be exposed in the environment for eliminating the possibility that the two generate the reaction, which is beneficial for raising the electrical property of the array substrate and realizing the signal conduction. In the array substrate, the signal transmission is smooth, and the substrate possesses the great electrical property.

Abstract: The invention provides an array substrate, each sub-pixel comprising: a control TFT and a pixel electrode connected to control TFT; the pixel electrode comprising: a main region pixel electrode and a secondary region pixel electrode, layout with a gap in-between, and a first connection electrode electrically connected to the main region pixel electrode and the secondary region pixel electrode; the main and secondary region pixel electrodes being of special shape slit structure, the main region branch electrodes having a width smaller than width of the secondary region branch electrodes, the main region slit having a width smaller than width of the secondary region slit. The structural difference in the main and secondary region pixel electrodes is used to improve color shift, leading to reducing the number of TFTs in each pixel, improving pixel aperture ratio, reduces difficulty in balance control of best common voltage between main and secondary regions.

Abstract: The present disclosure provides a Fringe Field Switching (FFS) mode array substrate and manufacturing method therefor. The array substrate comprises a plurality of scanning lines, a plurality of data lines, and a common electrode. The array substrate further comprises a plurality of conductive strips disposed between the scanning lines and the common electrode, and electrically connected to the common electrode, for conducting electric signal of the common electrode. The array substrate can keep the electric signal on the common electrode the same, and improve the display effect of the liquid crystal panel using the array substrate.

Abstract: The disclosure provides an array substrate, including a substrate, a common line, a separation layer, a gate line layer, a first insulation layer, a data line layer, a second insulation layer, a first transparent electrode, a third insulation layer and a second transparent electrode overlapped in sequence, a first via hole is defined in the separation layer, a second via hole is defined in the first insulation layer, a third via hole and a fourth via hole communicated with the second via hole are defined in the second insulation layer, the first transparent electrode penetrates the first via hole, the second via hole and the fourth via hole to connect with the common line, a fifth via hole communicated with the third via hole is defined in the third insulation layer, the second transparent electrode is connected to the data line layer.

Abstract: A panel inspection circuit is provided and includes: multiple data signal lines; multiple testing switches; multiple testing lines including: a first testing line, a second testing line and a third testing line; and multiple control lines including a first control line, a second control line and a third control line; the first control line is used to turn on the testing switches which are connected to the first testing line; the second control line is used to turn on the testing switches which are connected to the second testing line; the third control line is used to turn on the testing switches which are connected to the third testing line.

Abstract: A pixel structure having a substrate, an insulating layer and a pixel electrode is disclosed. The pixel electrode has first sub-electrodes and second sub-electrodes. The first sub-electrodes are arranged on a first region of the insulating layer and spaced apart from each other, and the second sub-electrodes are continuously disposed on a second region of the insulating layer. The first region is a flat region of the insulating layer, and the second region is a grooved region of the insulating layer.

Abstract: The present invention provides a manufacture method of an array substrate and an array substrate manufactured by the method. By employing one mask to achieve the via opening process to the flat layer and the first passivation layer, one mask can be saved to decrease the production cost and to reduce the process time; the conductive connection layer covering the first via on the flat layer and the second via on the first passivation layer are formed at the same time while forming the common electrode, and thus to prevent that the source/the drain and the flat layer to be exposed in the environment for eliminating the possibility that the two generate the reaction, which is beneficial for raising the electrical property of the array substrate and realizing the signal conduction. In the array substrate, the signal transmission is smooth, and the substrate possesses the great electrical property.

Abstract: The present invention provides a manufacture method of an array substrate and an array substrate manufactured by the method. By sequentially forming the first passivation layer and the flat layer, and then implementing patterning process and anneal process to the flat layer, in the anneal process to the flat layer, the flat layer and the source/the drain cannot contact with each other due to the first passivation layer inbetween, and thus, no reaction of generating complex happens, which is beneficial for promoting the electrical property of the array substrate and realizing the signal conduction; in comparison with prior art, the present invention can decrease at least one mask in advance, which is a advantage to raise the process result, to decrease the process time and to reduce the production cost. In the array substrate, the signal transmission is smooth, and the substrate possesses the great electrical property.