Abstract: A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric reactant; and a sealant layer arranged on a surface of the self-destructive layer, on sidewalls of the self-destructive layer, and on the chip substrate such that the sealant layer forms a package seal on the semiconductor chip; wherein the pyrophoric reactant ignites spontaneously upon exposure to air.

Abstract: Semiconductor devices and methods of making the same include forming a gate structure on a thin semiconductor layer. Additional semiconductor material is formed on the thin semiconductor layer. The thin semiconductor layer is etched back and the additional semiconductor material to form source and drain regions and a channel region, with notches separating the source and drain region from the channel region.

Abstract: The present disclosure provides a method of forming a biocompatible structure that includes forming biodissolvable substrate comprising a flexible network of peptides, and a biocompatible structure having a biodissolvable substrate and, optionally, an electronic device on a surface thereof for use in implantable electronics.

Abstract: A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90° with respect to the substrate.

Abstract: A sensor includes a semiconductor substrate having first pointed nodes extending into a channel from a first side of the channel. Second pointed nodes extend into the channel from a second side of the channel, which is opposite the first side. The second pointed nodes being self-aligned to the first pointed nodes on the opposite side of the channel. The first pointed nodes and the second pointed nodes are connected to a circuit to detect particles in the channel.

Abstract: An integrated circuit includes an array of devices including a physically unclonable function (PUF) for chip authentication. A logic pattern is stored in the devices. The logic pattern is determined in accordance with processing variations during manufacture of the array. The logic pattern is represented with a first state for one or more devices with contact shorts and a second state with one or more devices without contact shorts.

Abstract: A sensor includes a semiconductor substrate having first pointed nodes extending into a channel from a first side of the channel. Second pointed nodes extend into the channel from a second side of the channel, which is opposite the first side. The second pointed nodes being self-aligned to the first pointed nodes on the opposite side of the channel. The first pointed nodes and the second pointed nodes are connected to a circuit to detect particles in the channel.

Abstract: Circuits which self-destruct under radiation are provided. In one aspect, a method for creating a radiation-sensitive circuit is provided. The method includes the step of: connecting an integrated circuit to a power supply and to a ground in parallel with at least one dosimeter device, wherein the dosimeter device is configured to change from being an insulator to being a conductor under radiation. Radiation-sensitive circuits are also provided.

Abstract: Vacuum transistors with carbon nanotube as the collector and/or emitter electrodes are provided. In one aspect, a method for forming a vacuum transistor includes the steps of: covering a substrate with an insulating layer; forming a back gate(s) in the insulating layer; depositing a gate dielectric over the back gate; forming a carbon nanotube layer on the gate dielectric; patterning the carbon nanotube layer to provide first/second portions thereof over first/second sides of the back gate, separated from one another by a gap G, which serve as emitter and collector electrodes; forming a vacuum channel in the gate dielectric; and forming metal contacts to the emitter and collector electrodes. Vacuum transistors are also provided.

Abstract: Resource sharing method and device are provided. The method includes: sending an access request to a second communication network through a target backhaul link of the second communication network by a resource sharing device when the access request is received from a terminal from a first communication network; sending the access request to the first communication network by the second communication network, for authenticating the terminal; sending QoS level information of the terminal to the second communication network by the first communication network when the terminal is authenticated, and sending access rejected information to the second communication network when the terminal is unauthenticated; providing services for the terminal according to the subscription QoS level information, or rejecting to provide services for the terminal according to the access rejected information.

Abstract: A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90° with respect to the substrate.

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

Abstract: An electromechanical device comprises a substrate structure, a set of electrodes, one or more anchor trenches, and one or more multi-faced components. For example, each of the one or more multi-faced components comprises an isolation region formed on a first portion of the surface of the component, a high resistance region formed on a second portion of the surface of the component, and a low resistance region formed on a third portion of the surface of the component. For example, the synapse device is configured to provide an analog resistive output, ranging between the high resistance region and the low resistance region, from at least one of the set of electrodes in response to a pulsed voltage input to at least another one of the set of electrodes.

Abstract: After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors.

Abstract: An electromechanical device comprises a substrate structure, a set of electrodes, one or more anchor trenches, and one or more multi-faced components. For example, each of the one or more multi-faced components comprises an isolation region formed on a first portion of the surface of the component, a high resistance region formed on a second portion of the surface of the component, and a low resistance region formed on a third portion of the surface of the component. For example, the synapse device is configured to provide an analog resistive output, ranging between the high resistance region and the low resistance region, from at least one of the set of electrodes in response to a pulsed voltage input to at least another one of the set of electrodes.

Abstract: Circuits which self-destruct under radiation are provided. In one aspect, a method for creating a radiation-sensitive circuit is provided. The method includes the step of: connecting an integrated circuit to a power supply and to a ground in parallel with at least one dosimeter device, wherein the dosimeter device is configured to change from being an insulator to being a conductor under radiation. Radiation-sensitive circuits are also provided.

Abstract: A semiconductor device includes a first dielectric layer formed from a thermally conductive dielectric material. Contacts are formed in the first dielectric layer, the planar contacts being spaced apart to form a gap therebetween. The thermally conductive dielectric material of the first dielectric layer is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed laterally across the gap between the planar contacts and in direct contact with at least the thermally conductive dielectric material in the gap.

Abstract: A nanofluidic structure including a semiconductor substrate and a dielectric layer positioned above and in contact with the semiconductor substrate. A first reservoir and a second reservoir are defined by the semiconductor substrate and the dielectric layer. The second reservoir is spaced apart from the first reservoir. Bottom passage fins protrude from the semiconductor substrate and extend from the first reservoir to the second reservoir. Top passage fins, above and spaced apart from the bottom passage fins, extend from the first reservoir to the second reservoir. Nanofluidic passages between the top and bottom fins connect the first reservoir and the second reservoir. Each of the nanofluidic passages includes a bottom wall, a top wall and sidewalls. The bottom wall is defined by a respective bottom passage fin. The top wall is defined by a respective top passage fin. The sidewalls are defined by the dielectric layer.

Abstract: Vacuum transistors with carbon nanotube as the collector and/or emitter electrodes are provided. In one aspect, a method for forming a vacuum transistor includes the steps of: covering a substrate with an insulating layer; forming a back gate(s) in the insulating layer; depositing a gate dielectric over the back gate; forming a carbon nanotube layer on the gate dielectric; patterning the carbon nanotube layer to provide first/second portions thereof over first/second sides of the back gate, separated from one another by a gap G, which serve as emitter and collector electrodes; forming a vacuum channel in the gate dielectric; and forming metal contacts to the emitter and collector electrodes. Vacuum transistors are also provided.

Abstract: A method includes forming a trench in a Silicon substrate; depositing metal on sidewalls and a bottom of the trench; annealing to react the metal with underlying Si and form metal silicide adjacent to sidewalls and bottom of the trench; removing unreacted metal and depositing a dielectric layer on the metal silicide, a metal layer over the dielectric layer and polysilicon to fill a remainder of the trench thereby forming top plate electrode of a MIM capacitor. The method further forms a transistor adjacent to a top of the trench, where the transistor is connected to the top plate electrode of the MIM capacitor via a strap interface that comprises a portion of the metal silicide layer at the top of the trench. The portion of the metal silicide layer can be disposed in an SOI layer, and silicide in the Si substrate forms a bottom plate of the capacitor.