Abstract: Physical location information for a specified user is corrected according to vehicle location and trajectory analysis. Vehicles, such as delivery vehicles, produce physical location information for the vehicle during delivery events to the specified user and a surrounding physical area. The physical location information for the vehicle is accessed to correct erroneous physical location information for the specified user.

Abstract: Physical location information for a specified user is corrected according to vehicle location and trajectory analysis. Vehicles, such as delivery vehicles, produce physical location information for the vehicle during delivery events to the specified user and a surrounding physical area. The physical location information for the vehicle is accessed to correct erroneous physical location information for the specified user.

Abstract: Physical location information for a specified user is corrected according to vehicle location and trajectory analysis. Vehicles, such as delivery vehicles, produce physical location information for the vehicle during delivery events to the specified user and a surrounding physical area. The physical location information for the vehicle is accessed to correct erroneous physical location information for the specified user.

Abstract: The present invention relates to an automobile urea tank produced using a forming method. The method includes the following steps: (a) producing an upper half casing and a lower half casing through an injection molding method; (b) after the upper half casing and the lower half casing are formed, assembling built-in parts of the upper half casing and the lower half casing; (c) welding the assembled upper half casing and the assembled lower half casing to form a whole; and (d) assembling components on surfaces of the upper half casing and the lower half casing. This method can improve design freedom of built-in elements of the tank body, and can save a lot of raw materials; the structure is simple and firm; moreover, the production efficiency is improved, and the production cycle is shortened.

Abstract: The present invention relates to an automobile urea tank and a forming method thereof. The method includes the following steps: 1) producing an upper half casing and a lower half casing through an injection molding method; 2) after the upper half casing and the lower half casing are formed, assembling built-in parts of the upper half casing and the lower half casing; 3) welding the assembled upper half casing and the assembled lower half casing to form a whole; and 4) assembling components on surfaces of the upper half casing and the lower half casing. This method can improve design freedom of built-in elements of the tank body, and can save a lot of raw materials; the structure is simple and firm; moreover, the production efficiency is improved, and the production cycle is shortened.

Abstract: The present invention relates to an automobile urea tank and a forming method thereof. The method includes the following steps: 1) producing an upper half casing and a lower half casing through an injection molding method; 2) after the upper half casing and the lower half casing are formed, assembling built-in parts of the upper half casing and the lower half casing; 3) welding the assembled upper half casing and the assembled lower half casing to form a whole; and 4) assembling components on surfaces of the upper half casing and the lower half casing. This method can improve design freedom of built-in elements of the tank body, and can save a lot of raw materials; the structure is simple and firm; moreover, the production efficiency is improved, and the production cycle is shortened.

Abstract: A message processing method and system. According to embodiments of the present invention, the preference of a user for messages may be determined based on actions of the user regarding those messages. The message is analyzed to determine one or more categories to which content of the messages belongs to. Thus, a matching degree between the user and a corresponding category may be determined or adjusted according to the preference of the user for the messages. Such a matching degree may be then used for filtering an incoming message. According to embodiments of the present invention, for each specific user, the information that a user is not interested in may be filtered in a more accurate and adaptive manner.

Abstract: A spring leaf and an overrunning clutch provided with the same are provided. The spring leaf is made up of a support strip (3-1), a clamping strip (3-2), and a connection beam (3-3). The support strip (3-1) supports a needle roller in suspension. The connection beam (3-3) connects the support strip (3-1) with the clamping strip (3-2). The main body of the clamping strip (3-2) is a straight strip (3-2-1), either end of which is provided with a V-shaped bended part (3-2-2). The overrunning clutch is provided with a retainer, multiple needle rollers, and multiple spring leaves. Mounting grooves for the spring leaves are respectively disposed at positions, corresponding to each crossbeam, on outer end surfaces of a first and a second annular end edge at both ends of a window hole of the retainer. The bottom of the mounting groove for the spring leaf is V-shaped when cut along an axial direction of the retainer.

Abstract: A spring leaf and an overrunning clutch provided with the same are provided. The spring leaf is made up of a support strip (3-1), a clamping strip (3-2), and a connection beam (3-3). The support strip (3-1) supports a needle roller in suspension. The connection beam (3-3) connects the support strip (3-1) with the clamping strip (3-2). The main body of the clamping strip (3-2) is a straight strip (3-2-1), either end of which is provided with a V-shaped bended part (3-2-2). The overrunning clutch is provided with a retainer, multiple needle rollers, and multiple spring leaves. Mounting grooves for the spring leaves are respectively disposed at positions, corresponding to each crossbeam, on outer end surfaces of a first and a second annular end edge at both ends of a window hole of the retainer. The bottom of the mounting groove for the spring leaf is V-shaped when cut along an axial direction of the retainer.

Abstract: An interconnect joint comprises a substrate (110), a solder resist layer (120) over the substrate, a solder resist opening (130) (having a top surface (131)) in the solder resist layer, a solder material (140) in the solder resist opening, and an electrically conducting structure (150) having a portion that extends into the solder material below the top of the solder resist opening.

Abstract: In an embodiment, an initialization extension device may provide an extended initialization period to enable a processor to configure a device, for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device may include a number of control registers that may be configured to default settings in a register initialization period commenced in response to a reset signal. The reset signal may also trigger an extension timer to countdown a timer extended initialization period. During the timer extended initialization period, the processor may write an extension control signal, e.g., an extension bit, to a register. An initialization extension unit may maintain the device in an initialization mode during the timer extended initialization period and/or while the register contains the extension control signal. The processor may configure the control registers for one or more operations the device may perform when it enters the operating mode.

Abstract: A DMA (Direct Memory Access) Exchange Block (DXB) processor may include a receive processor for writing data from a local memory to a host memory over a bus, e.g., a Peripheral Component Interconnect Extended (PCI/X) bus, and a transmit processor for writing data retrieved from the host memory over the bus to the local memory. Each processor may include a high priority queue and a normal priority queue. A controlling program generates DXBs, each of which include a tag assigned by the controlling program and memory descriptors corresponding to a direct memory access operation. The memory descriptor may include a host memory descriptor (address/length) and one or more local memory descriptors. The controlling program writes a DXB to one of the queues in a cache line spill operation. The transfer processor may include two channel registers, enabling the processor to perform two PCI/X data transfers simultaneously.

Abstract: A memory controller for a multi-byte burst memory device may control access to memory based on parameters set up by a client. These parameters may include a byte address and a byte count that indicates the number of bytes the client is requesting from memory. These values, and an integer representing the number of bytes in a burst-accessed word, may be operated on to produce a word that may be used to identify valid bytes in the burst-accessed word.

Abstract: The present invention is directed to a memory data interface for transferring data between a memory device and an integrated circuit, whereby, in accordance with one aspect of the present invention, the memory data interface includes a data selector for selecting and normalizing data from memory devices operating at different data transfer timing, and, in accordance with another aspect of the present invention, the memory data interface is capable of transferring data between a memory device and an integrated circuit having a different bus width than the memory device. In accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of different memory device having different data bus widths.

Abstract: The present invention is directed to a memory data interface for transferring data between a memory device and an integrated circuit, whereby, in accordance with one aspect of the present invention, the memory data interface includes a data selector for selecting and normalizing data from memory devices operating at different data transfer timing, and, in accordance with another aspect of the present invention, the memory data interface is capable of transferring data between a memory device and an integrated circuit having a different bus width than the memory device. In accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of different memory device having different data bus widths.

Abstract: In an embodiment, an initialization extension device may provide an extended initialization period to enable a processor to configure a device, for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device may include a number of control registers that may be configured to default settings in a register initialization period commenced in response to a reset signal. The reset signal may also trigger an extension timer to countdown a timer extended initialization period. During the timer extended initialization period, the processor may write an extension control signal, e.g., an extension bit, to a register. An initialization extension unit may maintain the device in an initialization mode during the timer extended initialization period and/or while the register contains the extension control signal. The processor may configure the control registers for one or more operations the device may perform when it enters the operating mode.

Abstract: In an embodiment, an initialization extension device may provide an extended initialization period to enable a processor to configure a device, for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device may include a number of control registers that may be configured to default settings in a register initialization period commenced in response to a reset signal. The reset signal may also trigger an extension timer to countdown a timer extended initialization period. During the timer extended initialization period, the processor may write an extension control signal, e.g., an extension bit, to a register. An initialization extension unit may maintain the device in an initialization mode during the timer extended initialization period and/or while the register contains the extension control signal. The processor may configure the control registers for one or more operations the device may perform when it enters the operating mode.

Abstract: A data formatter includes a shift register and a pointer manager. The shift register receives data from a providing RAM and shifts that data in response to reading data from the providing RAM and writing data to a receiving FIFO. A pointer manager maintains a pointer that points to a first valid byte in a sub-block of data into the correct bytes lanes of the FIFO by moving the pointer as data is shifted into and out of the shift register.

Abstract: A hub port in a Fiber Channel loop includes a hub data source, a loop initialization data detect circuit, and a loop initialization counter. The hub data source supplies data to the hub port from the Fiber Channel loop. The loop initialization data detect circuit is configured to detect valid loop initialization sequences from an attached node port and the hub data source. The loop initialization counter is configured to increment a count value of the valid loop initialization sequence from the attached node port if the loop initialization sequence from the node port does not match the valid loop initialization sequence from the hub data source. This state indicates that the loop initialization sequence is initiated by the attached node port.

Abstract: A DMA (Direct Memory Access) Exchange Block (DXB) processor may include a receive processor for writing data from a local memory to a host memory over a bus, e.g., a Peripheral Component Interconnect Extended (PCI/X) bus, and a transmit processor for writing data retrieved from the host memory over the bus to the local memory. Each processor may include a high priority queue and a normal priority queue. A controlling program generates DXBs, each of which include a tag assigned by the controlling program and memory descriptors corresponding to a direct memory access operation. The memory descriptor may include a host memory descriptor (address/length) and one or more local memory descriptors. The controlling program writes a DXB to one of the queues in a cache line spill operation. The transfer processor may include two channel registers, enabling the processor to perform two PCI/X data transfers simultaneously.