Patents by Inventor Qingchun Zhang

Qingchun Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11075264
    Abstract: Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/?1.5° of a crystallographic axis of the silicon carbide material forming the drift region.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 27, 2021
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Alexander V. Suvorov, Vipindas Pala, Daniel J. Lichtenwalner, Qingchun Zhang
  • Patent number: 11024731
    Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: June 1, 2021
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
  • Publication number: 20210155710
    Abstract: Provided herein are methods of modulating Antibody Dependent Cellular Phagocytosis (ADCP) activity of an antibody composition. In exemplary embodiments, the method comprises modulating the amount of (a) galactosylated glycans of the antibody, (b) afucosylated glycans of the antibody, (c) high mannose glycans of the antibody, or (d) a combination thereof, to modulate ADCP activity of the antibody, as further described herein.
    Type: Application
    Filed: June 5, 2019
    Publication date: May 27, 2021
    Inventors: Scott KUHNS, Junyan SHU, Qingchun ZHANG
  • Publication number: 20210093375
    Abstract: An ablation lesion assessment method and system for obtaining ablation information by analyzing an intracardiac electrode signal from an ablation lesion are disclosed. The ablation lesion assessment system includes: a baseline calculation unit for generating a baseline for a signal profile and calculating a proportion of portions of the signal profile located above the baseline in the whole signal profile; a waveform comparison unit for obtaining a waveform comparison result by comparing the signal profile with an ablation pattern; and a determining unit for making a determination based on the proportion and the waveform comparison result and outputting the ablation information that indicates whether complete ablation has been achieved. The ablation lesion assessment method can utilize the ablation lesion assessment system to obtain the ablation information that indicates whether complete ablation has been achieved.
    Type: Application
    Filed: April 24, 2019
    Publication date: April 1, 2021
    Inventors: Huimin CHU, Huasheng CHENG, Qingchun ZHANG, Yahui PENG, Liuping SHEN, Yiyong SUN
  • Publication number: 20210066462
    Abstract: Semiconductor structures and fabrication methods thereof are provided. The method includes: providing a substrate, the substate having a first opening; forming a first epitaxial layer in the first opening, the first epitaxial layer having a second opening; forming a stop layer on sidewall surfaces and a bottom surface of the second opening; forming a second epitaxial layer on a top surface of the stop layer; after forming the second epitaxial layer, forming a dielectric layer on the substrate, the dielectric layer having a third opening exposing a surface of the second epitaxial layer; forming a fourth opening in the second epitaxial layer by etching the second epitaxial layer exposed by the third opening until the stop layer is exposed; and forming a contact layer on sidewall surfaces and a bottom surface of the fourth opening by performing a semiconductor metallization process.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 4, 2021
    Inventor: Qingchun ZHANG
  • Patent number: 10886396
    Abstract: A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: January 5, 2021
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Patent number: 10847645
    Abstract: A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 24, 2020
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Patent number: 10840367
    Abstract: A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: November 17, 2020
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Publication number: 20200212908
    Abstract: Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Inventors: Qingchun Zhang, Adam Barkley, Sei-Hyung Ryu, Brett Hull
  • Patent number: 10601413
    Abstract: Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 24, 2020
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Adam Barkley, Sei-Hyung Ryu, Brett Hull
  • Patent number: 10510905
    Abstract: A Schottky diode includes a drift region, a channel in an upper portion of the drift region, and first and second adjacent blocking junctions in the upper portion of the drift region that define the channel therebetween. The drift region and channel are doped with dopants having a first conductivity type, and the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type. The blocking junctions extend at least one micron into the upper portion of the drift region and are spaced apart from each other by less than 3.0 microns.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 17, 2019
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Edward R. Van Brunt, Brett Hull, Scott Thomas Allen
  • Publication number: 20190371931
    Abstract: A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
    Type: Application
    Filed: August 12, 2019
    Publication date: December 5, 2019
    Inventors: Qingchun Zhang, Alexander V. Suvorov
  • Patent number: 10424660
    Abstract: A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 24, 2019
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Alexander V. Suvorov
  • Patent number: 10403553
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a high dielectric constant (high-k) gate dielectric layer on the semiconductor substrate, the high-k gate dielectric layer including a nitrided surface that has been subjected to a nitriding treatment or an oxidized surface that has been subjected to an oxidizing treatment, forming a metal gate on the nitrided surface of the high-k gate dielectric layer to form an NMOS transistor, or forming a metal gate on the oxidized surface of the high-k gate dielectric layer to form a PMOS transistor.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: September 3, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Qingchun Zhang
  • Publication number: 20190198656
    Abstract: A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Qingchun Zhang, Alexander V. Suvorov
  • Publication number: 20190081624
    Abstract: Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Inventors: Qingchun Zhang, Adam Barkley, Sei-Hyung Ryu, Brett Hull
  • Publication number: 20190067468
    Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.
    Type: Application
    Filed: October 26, 2018
    Publication date: February 28, 2019
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
  • Publication number: 20190043980
    Abstract: A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.
    Type: Application
    Filed: October 1, 2018
    Publication date: February 7, 2019
    Inventors: Qingchun Zhang, Brett Hull
  • Publication number: 20190013416
    Abstract: A Schottky diode includes a drift region, a channel in an upper portion of the drift region, and first and second adjacent blocking junctions in the upper portion of the drift region that define the channel therebetween. The drift region and channel are doped with dopants having a first conductivity type, and the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type. The blocking junctions extend at least one micron into the upper portion of the drift region and are spaced apart from each other by less than 3.0 microns.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 10, 2019
    Inventors: Qingchun Zhang, Edward R. Van Brunt, Brett Hull, Scott Thomas Allen
  • Patent number: 10153364
    Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 11, 2018
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen