Patents by Inventor Qingchun Zhang

Qingchun Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847645
    Abstract: A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 24, 2020
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Patent number: 10840367
    Abstract: A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: November 17, 2020
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Publication number: 20200212908
    Abstract: Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Inventors: Qingchun Zhang, Adam Barkley, Sei-Hyung Ryu, Brett Hull
  • Patent number: 10601413
    Abstract: Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 24, 2020
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Adam Barkley, Sei-Hyung Ryu, Brett Hull
  • Patent number: 10510905
    Abstract: A Schottky diode includes a drift region, a channel in an upper portion of the drift region, and first and second adjacent blocking junctions in the upper portion of the drift region that define the channel therebetween. The drift region and channel are doped with dopants having a first conductivity type, and the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type. The blocking junctions extend at least one micron into the upper portion of the drift region and are spaced apart from each other by less than 3.0 microns.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 17, 2019
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Edward R. Van Brunt, Brett Hull, Scott Thomas Allen
  • Publication number: 20190371931
    Abstract: A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
    Type: Application
    Filed: August 12, 2019
    Publication date: December 5, 2019
    Inventors: Qingchun Zhang, Alexander V. Suvorov
  • Patent number: 10424660
    Abstract: A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 24, 2019
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Alexander V. Suvorov
  • Patent number: 10403553
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a high dielectric constant (high-k) gate dielectric layer on the semiconductor substrate, the high-k gate dielectric layer including a nitrided surface that has been subjected to a nitriding treatment or an oxidized surface that has been subjected to an oxidizing treatment, forming a metal gate on the nitrided surface of the high-k gate dielectric layer to form an NMOS transistor, or forming a metal gate on the oxidized surface of the high-k gate dielectric layer to form a PMOS transistor.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: September 3, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Qingchun Zhang
  • Publication number: 20190198656
    Abstract: A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Qingchun Zhang, Alexander V. Suvorov
  • Publication number: 20190081624
    Abstract: Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Inventors: Qingchun Zhang, Adam Barkley, Sei-Hyung Ryu, Brett Hull
  • Publication number: 20190067468
    Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.
    Type: Application
    Filed: October 26, 2018
    Publication date: February 28, 2019
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
  • Publication number: 20190043980
    Abstract: A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.
    Type: Application
    Filed: October 1, 2018
    Publication date: February 7, 2019
    Inventors: Qingchun Zhang, Brett Hull
  • Publication number: 20190013416
    Abstract: A Schottky diode includes a drift region, a channel in an upper portion of the drift region, and first and second adjacent blocking junctions in the upper portion of the drift region that define the channel therebetween. The drift region and channel are doped with dopants having a first conductivity type, and the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type. The blocking junctions extend at least one micron into the upper portion of the drift region and are spaced apart from each other by less than 3.0 microns.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 10, 2019
    Inventors: Qingchun Zhang, Edward R. Van Brunt, Brett Hull, Scott Thomas Allen
  • Patent number: 10153364
    Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 11, 2018
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
  • Patent number: 10115815
    Abstract: A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SIC) MOSFET device.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 30, 2018
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Publication number: 20180211886
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a high dielectric constant (high-k) gate dielectric layer on the semiconductor substrate, the high-k gate dielectric layer including a nitrided surface that has been subjected to a nitriding treatment or an oxidized surface that has been subjected to an oxidizing treatment, forming a metal gate on the nitrided surface of the high-k gate dielectric layer to form an NMOS transistor, or forming a metal gate on the oxidized surface of the high-k gate dielectric layer to form a PMOS transistor.
    Type: Application
    Filed: January 16, 2018
    Publication date: July 26, 2018
    Inventor: Qingchun Zhang
  • Patent number: 9991399
    Abstract: A Schottky diode is disclosed that includes a silicon carbide substrate, a silicon carbide drift layer, a Schottky contact, and a passivation structure. The silicon carbide drift layer provides an active region and an edge termination region about the active region. The Schottky contact has sides and a top extending between the two sides and includes a Schottky layer over the active region and an anode contact over the Schottky layer. The passivation structure covers the edge termination region, the sides of the Schottky contact, and at least a portion of the top of the Schottky contact. The passivation structure includes a first silicon nitride layer, a silicon dioxide layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon dioxide layer.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 5, 2018
    Assignee: Cree, Inc.
    Inventors: Van Mieczkowski, Jonathan Young, Qingchun Zhang, John Williams Palmour
  • Patent number: 9941439
    Abstract: A thyristor includes a first conductivity type semiconductor layer, a first conductivity type carrier injection layer on the semiconductor layer, a second conductivity type drift layer on the carrier injection layer, a first conductivity type base layer on the drift layer, and a second conductivity type anode region on the base layer. The thickness and doping concentration of the carrier injection layer are selected to reduce minority carrier injection by the carrier injection layer in response to an increase in operating temperature of the thyristor. A cross-over current density at which the thyristor shifts from a negative temperature coefficient of forward voltage to a positive temperature coefficient of forward voltage is thereby reduced.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: April 10, 2018
    Assignee: Cree, Inc.
    Inventor: Qingchun Zhang
  • Patent number: 9929284
    Abstract: A Schottky diode includes a drift region doped with dopants having a first conductivity type, first and second blocking junctions that are doped with dopants having a second conductivity type in an upper portion of the drift region, first and second local current spreading layers doped with dopants having the first conductivity type underneath the respective first and second blocking junctions, and first and second contacts on respective lower and upper portions of the drift region. A channel is provided in the upper portion of the drift region between the first and second blocking junctions, the channel doped with dopants having the first conductivity type and a concentration of dopants in at least a first portion of the channel being lower than the concentration of dopants in the first and second local current spreading layers.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: March 27, 2018
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Alexander Suvorov
  • Patent number: 9865750
    Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: January 9, 2018
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen